From 139787f426f735c96ddea2acd166b8127799ae9f Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Thu, 7 Jul 2016 14:01:15 +0800 Subject: [PATCH] arm64: dts: berlin4ct: Add L2 cache topology This patch adds the L2 cache topology for berlin4ct which has 1MB L2 cache. [Sebastian: rename cache node from "l2-cache" to "cache"] Signed-off-by: Jisheng Zhang Signed-off-by: Sebastian Hesselbarth --- arch/arm64/boot/dts/marvell/berlin4ct.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi index 0af4780530b8..85c23facb9fe 100644 --- a/arch/arm64/boot/dts/marvell/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/marvell/berlin4ct.dtsi @@ -68,6 +68,7 @@ device_type = "cpu"; reg = <0x0>; enable-method = "psci"; + next-level-cache = <&l2>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -76,6 +77,7 @@ device_type = "cpu"; reg = <0x1>; enable-method = "psci"; + next-level-cache = <&l2>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -84,6 +86,7 @@ device_type = "cpu"; reg = <0x2>; enable-method = "psci"; + next-level-cache = <&l2>; cpu-idle-states = <&CPU_SLEEP_0>; }; @@ -92,9 +95,14 @@ device_type = "cpu"; reg = <0x3>; enable-method = "psci"; + next-level-cache = <&l2>; cpu-idle-states = <&CPU_SLEEP_0>; }; + l2: cache { + compatible = "cache"; + }; + idle-states { entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 {