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arm64: dts: berlin4ct: Add L2 cache topology 

This patch adds the L2 cache topology for berlin4ct which has 1MB L2
cache.

[Sebastian: rename cache node from "l2-cache" to "cache"]

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This commit is contained in:
Jisheng Zhang 2016-07-07 14:01:15 +08:00 committed by Sebastian Hesselbarth
parent 7091eb9699
commit 139787f426
1 changed files with 8 additions and 0 deletions
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8
arch/arm64/boot/dts/marvell/berlin4ct.dtsi
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@ -68,6 +68,7 @@
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
@ -76,6 +77,7 @@
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
@ -84,6 +86,7 @@
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
@ -92,9 +95,14 @@
device_type = "cpu";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_SLEEP_0>;
};
l2: cache {
compatible = "cache";
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {