qed: Add abstraction for different hsi values per chip
The number of BTB blocks was modified to be different between the two chip flavors supported (BB/K2) as a result, this lead to a re-write of selecting the default hsi value based on the chip. This patch creates a lookup table for hsi values per chip rather than ask again and again for every value. Signed-off-by: Ariel Elior <ariel.elior@marvell.com> Signed-off-by: Michal Kalderon <michal.kalderon@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -532,6 +532,23 @@ struct qed_nvm_image_info {
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bool valid;
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};
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enum qed_hsi_def_type {
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QED_HSI_DEF_MAX_NUM_VFS,
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QED_HSI_DEF_MAX_NUM_L2_QUEUES,
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QED_HSI_DEF_MAX_NUM_PORTS,
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QED_HSI_DEF_MAX_SB_PER_PATH,
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QED_HSI_DEF_MAX_NUM_PFS,
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QED_HSI_DEF_MAX_NUM_VPORTS,
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QED_HSI_DEF_NUM_ETH_RSS_ENGINE,
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QED_HSI_DEF_MAX_QM_TX_QUEUES,
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QED_HSI_DEF_NUM_PXP_ILT_RECORDS,
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QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
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QED_HSI_DEF_MAX_QM_GLOBAL_RLS,
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QED_HSI_DEF_MAX_PBF_CMD_LINES,
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QED_HSI_DEF_MAX_BTB_BLOCKS,
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QED_NUM_HSI_DEFS
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};
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#define DRV_MODULE_VERSION \
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__stringify(QED_MAJOR_VERSION) "." \
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__stringify(QED_MINOR_VERSION) "." \
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@ -869,16 +886,35 @@ struct qed_dev {
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bool iwarp_cmt;
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};
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#define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \
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: MAX_NUM_VFS_K2)
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#define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \
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: MAX_NUM_L2_QUEUES_K2)
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#define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \
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: MAX_NUM_PORTS_K2)
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#define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \
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: MAX_SB_PER_PATH_K2)
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#define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \
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: MAX_NUM_PFS_K2)
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u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type);
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#define NUM_OF_VFS(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS)
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#define NUM_OF_L2_QUEUES(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES)
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#define NUM_OF_PORTS(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS)
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#define NUM_OF_SBS(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH)
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#define NUM_OF_ENG_PFS(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS)
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#define NUM_OF_VPORTS(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS)
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#define NUM_OF_RSS_ENGINES(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE)
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#define NUM_OF_QM_TX_QUEUES(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES)
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#define NUM_OF_PXP_ILT_RECORDS(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS)
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#define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
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#define NUM_OF_QM_GLOBAL_RLS(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS)
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#define NUM_OF_PBF_CMD_LINES(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES)
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#define NUM_OF_BTB_BLOCKS(dev) \
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qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)
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/**
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* @brief qed_concrete_to_sw_fid - get the sw function id from
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@ -1579,6 +1579,7 @@ static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
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{
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/* Initialize qm port parameters */
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u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine;
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struct qed_dev *cdev = p_hwfn->cdev;
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/* indicate how ooo and high pri traffic is dealt with */
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active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ?
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@ -1588,11 +1589,13 @@ static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn)
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for (i = 0; i < num_ports; i++) {
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struct init_qm_port_params *p_qm_port =
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&p_hwfn->qm_info.qm_port_params[i];
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u16 pbf_max_cmd_lines;
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p_qm_port->active = 1;
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p_qm_port->active_phys_tcs = active_phys_tcs;
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p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
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p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
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pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev);
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p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports;
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p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports;
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}
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}
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@ -3607,14 +3610,39 @@ __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn,
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return 0;
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}
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static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = {
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{MAX_NUM_VFS_BB, MAX_NUM_VFS_K2},
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{MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2},
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{MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2},
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{MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,},
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{MAX_NUM_PFS_BB, MAX_NUM_PFS_K2},
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{MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2},
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{ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2},
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{MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2},
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{PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2},
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{RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2},
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{MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS},
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{PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES},
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{BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2},
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};
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u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type)
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{
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enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2;
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if (type >= QED_NUM_HSI_DEFS) {
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DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type);
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return 0;
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}
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return qed_hsi_def_val[type][chip_id];
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}
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static int
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qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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{
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bool b_ah = QED_IS_AH(p_hwfn->cdev);
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u32 resc_max_val, mcp_resp;
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u8 res_id;
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int rc;
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for (res_id = 0; res_id < QED_MAX_RESC; res_id++) {
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switch (res_id) {
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case QED_LL2_RAM_QUEUE:
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@ -3630,8 +3658,8 @@ qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
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resc_max_val = NUM_OF_GLOBAL_QUEUES;
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break;
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case QED_RDMA_STATS_QUEUE:
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resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2
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: RDMA_NUM_STATISTIC_COUNTERS_BB;
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resc_max_val =
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NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev);
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break;
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case QED_BDQ:
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resc_max_val = BDQ_NUM_RESOURCES;
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@ -3664,28 +3692,24 @@ int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
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u32 *p_resc_num, u32 *p_resc_start)
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{
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u8 num_funcs = p_hwfn->num_funcs_on_engine;
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bool b_ah = QED_IS_AH(p_hwfn->cdev);
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struct qed_dev *cdev = p_hwfn->cdev;
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switch (res_id) {
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case QED_L2_QUEUE:
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*p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 :
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MAX_NUM_L2_QUEUES_BB) / num_funcs;
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*p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs;
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break;
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case QED_VPORT:
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*p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 :
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MAX_NUM_VPORTS_BB) / num_funcs;
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*p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs;
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break;
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case QED_RSS_ENG:
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*p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 :
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ETH_RSS_ENGINE_NUM_BB) / num_funcs;
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*p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs;
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break;
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case QED_PQ:
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*p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 :
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MAX_QM_TX_QUEUES_BB) / num_funcs;
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*p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs;
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*p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */
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break;
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case QED_RL:
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*p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs;
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*p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs;
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break;
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case QED_MAC:
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case QED_VLAN:
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@ -3693,8 +3717,7 @@ int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
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*p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs;
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break;
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case QED_ILT:
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*p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 :
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PXP_NUM_ILT_RECORDS_BB) / num_funcs;
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*p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs;
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break;
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case QED_LL2_RAM_QUEUE:
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*p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs;
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@ -3708,8 +3731,7 @@ int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn,
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*p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs;
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break;
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case QED_RDMA_STATS_QUEUE:
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*p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 :
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RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs;
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*p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs;
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break;
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case QED_BDQ:
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if (p_hwfn->hw_info.personality != QED_PCI_ISCSI &&
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@ -663,8 +663,8 @@
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#define PBF_MAX_CMD_LINES 3328
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/* Number of BTB blocks. Each block is 256B. */
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#define BTB_MAX_BLOCKS 1440
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#define BTB_MAX_BLOCKS_BB 1440
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#define BTB_MAX_BLOCKS_K2 1840
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/*****************/
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/* PRS CONSTANTS */
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/*****************/
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