dmaengine: at_xdmac: Fix lld view setting
AT_XDMAC_CNDC_NDVIEW_NDV3 was set even for AT_XDMAC_MBR_UBC_NDV2,
because of the wrong bit handling. Fix it.
Fixes: ee0fe35c8d
("dmaengine: xdmac: Handle descriptor's view 3 registers")
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20211215110115.191749-10-tudor.ambarus@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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@ -99,6 +99,7 @@
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#define AT_XDMAC_CNDC_NDE (0x1 << 0) /* Channel x Next Descriptor Enable */
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#define AT_XDMAC_CNDC_NDSUP (0x1 << 1) /* Channel x Next Descriptor Source Update */
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#define AT_XDMAC_CNDC_NDDUP (0x1 << 2) /* Channel x Next Descriptor Destination Update */
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#define AT_XDMAC_CNDC_NDVIEW_MASK GENMASK(28, 27)
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#define AT_XDMAC_CNDC_NDVIEW_NDV0 (0x0 << 3) /* Channel x Next Descriptor View 0 */
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#define AT_XDMAC_CNDC_NDVIEW_NDV1 (0x1 << 3) /* Channel x Next Descriptor View 1 */
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#define AT_XDMAC_CNDC_NDVIEW_NDV2 (0x2 << 3) /* Channel x Next Descriptor View 2 */
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@ -402,7 +403,8 @@ static void at_xdmac_start_xfer(struct at_xdmac_chan *atchan,
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*/
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if (at_xdmac_chan_is_cyclic(atchan))
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reg = AT_XDMAC_CNDC_NDVIEW_NDV1;
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else if (first->lld.mbr_ubc & AT_XDMAC_MBR_UBC_NDV3)
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else if ((first->lld.mbr_ubc &
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AT_XDMAC_CNDC_NDVIEW_MASK) == AT_XDMAC_MBR_UBC_NDV3)
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reg = AT_XDMAC_CNDC_NDVIEW_NDV3;
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else
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reg = AT_XDMAC_CNDC_NDVIEW_NDV2;
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