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clk: xgene: Fix divider with non-zero shift value 

The X-Gene clock driver missed the divider shift operation when
set the divider value.

Signed-off-by: Loc Ho <lho@apm.com>
Fixes: 308964caee ("clk: Add APM X-Gene SoC clock driver")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Loc Ho 2015-11-19 12:20:30 -07:00 committed by Stephen Boyd
parent 6dc669a22c
commit 1382ea631d
1 changed files with 2 additions and 1 deletions
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3
drivers/clk/clk-xgene.c
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@ -351,7 +351,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
/* Set new divider */
data = xgene_clk_read(pclk->param.divider_reg +
pclk->param.reg_divider_offset);
data &= ~((1 << pclk->param.reg_divider_width) - 1);
data &= ~((1 << pclk->param.reg_divider_width) - 1)
<< pclk->param.reg_divider_shift;
data |= divider;
xgene_clk_write(data, pclk->param.divider_reg +
pclk->param.reg_divider_offset);