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drm/amd/display: Change how we disable pipe split 

Before this change, pipe split was disabled by bumping up dpp clock
bounding box for DPM level 0 and 1, this allows validation to pass
without splitting at a lower DPM level. This change reverts this
and instead lowers display clock at DPM level 0, this forces
configurations that need pipe split at DPM level 0 to go to
DPM level 1, where they can be driven without split.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Yang 2017-07-05 15:30:18 -04:00 committed by Alex Deucher
parent 966443b592
commit 133e8e1b35
1 changed files with 1 additions and 2 deletions
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3
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
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@ -822,8 +822,7 @@ bool dcn_validate_bandwidth(
v->phyclk_per_state[0] = v->phyclkv_min0p65;
if (dc->public.debug.disable_pipe_split) {
v->max_dppclk[1] = v->max_dppclk_vnom0p8;
v->max_dppclk[0] = v->max_dppclk_vnom0p8;
v->max_dispclk[0] = v->max_dppclk_vmin0p65;
}
if (v->voltage_override == dcn_bw_v_max0p9) {