Blackfin: improve async bank access checking (for cross-banks & XIP)
The access_ok() function did not accept ranges within the async banks which made it impossible to do XIP in flash. Fixing that also showed that the current bfin_mem_access_type() code did not work with accesses that spanned async banks (like a file system). So split out and fix the async bank checks so that all these scenarios work as expected. Signed-off-by: Bernd Schmidt <bernds_cb1@t-online.de> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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@ -332,12 +332,58 @@ int in_mem_const(unsigned long addr, unsigned long size,
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{
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return in_mem_const_off(addr, size, 0, const_addr, const_size);
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}
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#define IN_ASYNC(bnum, bctlnum) \
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#define ASYNC_ENABLED(bnum, bctlnum) \
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({ \
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(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? -EFAULT : \
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bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? -EFAULT : \
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BFIN_MEM_ACCESS_CORE; \
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(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
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bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
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1; \
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})
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/*
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* We can't read EBIU banks that aren't enabled or we end up hanging
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* on the access to the async space. Make sure we validate accesses
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* that cross async banks too.
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* 0 - found, but unusable
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* 1 - found & usable
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* 2 - not found
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*/
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static
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int in_async(unsigned long addr, unsigned long size)
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{
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if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
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if (!ASYNC_ENABLED(0, 0))
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return 0;
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if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
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return 1;
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size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
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addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
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}
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if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
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if (!ASYNC_ENABLED(1, 0))
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return 0;
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if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
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return 1;
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size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
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addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
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}
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if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
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if (!ASYNC_ENABLED(2, 1))
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return 0;
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if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
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return 1;
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size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
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addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
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}
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if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
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if (ASYNC_ENABLED(3, 1))
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return 0;
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if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
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return 1;
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return 0;
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}
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/* not within async bounds */
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return 2;
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}
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int bfin_mem_access_type(unsigned long addr, unsigned long size)
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{
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@ -374,17 +420,11 @@ int bfin_mem_access_type(unsigned long addr, unsigned long size)
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if (addr >= SYSMMR_BASE)
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return BFIN_MEM_ACCESS_CORE_ONLY;
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/* We can't read EBIU banks that aren't enabled or we end up hanging
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* on the access to the async space.
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*/
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if (in_mem_const(addr, size, ASYNC_BANK0_BASE, ASYNC_BANK0_SIZE))
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return IN_ASYNC(0, 0);
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if (in_mem_const(addr, size, ASYNC_BANK1_BASE, ASYNC_BANK1_SIZE))
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return IN_ASYNC(1, 0);
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if (in_mem_const(addr, size, ASYNC_BANK2_BASE, ASYNC_BANK2_SIZE))
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return IN_ASYNC(2, 1);
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if (in_mem_const(addr, size, ASYNC_BANK3_BASE, ASYNC_BANK3_SIZE))
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return IN_ASYNC(3, 1);
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switch (in_async(addr, size)) {
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case 0: return -EFAULT;
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case 1: return BFIN_MEM_ACCESS_CORE;
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case 2: /* fall through */;
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}
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if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
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return BFIN_MEM_ACCESS_CORE;
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@ -401,6 +441,8 @@ __attribute__((l1_text))
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/* Return 1 if access to memory range is OK, 0 otherwise */
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int _access_ok(unsigned long addr, unsigned long size)
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{
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int aret;
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if (size == 0)
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return 1;
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/* Check that things do not wrap around */
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@ -450,6 +492,11 @@ int _access_ok(unsigned long addr, unsigned long size)
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if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
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return 1;
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#endif
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aret = in_async(addr, size);
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if (aret < 2)
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return aret;
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if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
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return 1;
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