drm/i915: Move reserve_seqno() next to unreserve_seqno()
Move the companion functions next to each other. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170223074422.4125-4-chris@chris-wilson.co.uk
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Chris Wilson
parent
9b6586ae9f
commit
12d3173b2e
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@ -198,6 +198,83 @@ i915_priotree_init(struct i915_priotree *pt)
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pt->priority = INT_MIN;
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}
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static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno)
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{
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struct i915_gem_timeline *timeline = &i915->gt.global_timeline;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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int ret;
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/* Carefully retire all requests without writing to the rings */
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ret = i915_gem_wait_for_idle(i915,
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I915_WAIT_INTERRUPTIBLE |
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I915_WAIT_LOCKED);
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if (ret)
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return ret;
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i915_gem_retire_requests(i915);
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GEM_BUG_ON(i915->gt.active_requests > 1);
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/* If the seqno wraps around, we need to clear the breadcrumb rbtree */
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for_each_engine(engine, i915, id) {
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struct intel_timeline *tl = &timeline->engine[id];
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if (!i915_seqno_passed(seqno, tl->seqno)) {
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/* spin until threads are complete */
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while (intel_breadcrumbs_busy(engine))
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cond_resched();
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}
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/* Finally reset hw state */
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tl->seqno = seqno;
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intel_engine_init_global_seqno(engine, seqno);
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}
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list_for_each_entry(timeline, &i915->gt.timelines, link) {
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for_each_engine(engine, i915, id) {
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struct intel_timeline *tl = &timeline->engine[id];
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memset(tl->sync_seqno, 0, sizeof(tl->sync_seqno));
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}
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}
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return 0;
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}
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int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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lockdep_assert_held(&dev_priv->drm.struct_mutex);
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if (seqno == 0)
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return -EINVAL;
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/* HWS page needs to be set less than what we
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* will inject to ring
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*/
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return reset_all_global_seqno(dev_priv, seqno - 1);
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}
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static int reserve_seqno(struct intel_engine_cs *engine)
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{
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u32 active = ++engine->timeline->inflight_seqnos;
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u32 seqno = engine->timeline->seqno;
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int ret;
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/* Reservation is fine until we need to wrap around */
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if (likely(!add_overflows(seqno, active)))
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return 0;
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ret = reset_all_global_seqno(engine->i915, 0);
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if (ret) {
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engine->timeline->inflight_seqnos--;
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return ret;
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}
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return 0;
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}
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static void unreserve_seqno(struct intel_engine_cs *engine)
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{
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GEM_BUG_ON(!engine->timeline->inflight_seqnos);
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@ -314,90 +391,6 @@ void i915_gem_request_retire_upto(struct drm_i915_gem_request *req)
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} while (tmp != req);
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}
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static int reset_all_global_seqno(struct drm_i915_private *i915, u32 seqno)
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{
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struct i915_gem_timeline *timeline = &i915->gt.global_timeline;
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struct intel_engine_cs *engine;
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enum intel_engine_id id;
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int ret;
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/* Carefully retire all requests without writing to the rings */
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ret = i915_gem_wait_for_idle(i915,
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I915_WAIT_INTERRUPTIBLE |
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I915_WAIT_LOCKED);
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if (ret)
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return ret;
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i915_gem_retire_requests(i915);
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GEM_BUG_ON(i915->gt.active_requests > 1);
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/* If the seqno wraps around, we need to clear the breadcrumb rbtree */
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for_each_engine(engine, i915, id) {
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struct intel_timeline *tl = &timeline->engine[id];
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if (!i915_seqno_passed(seqno, tl->seqno)) {
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/* spin until threads are complete */
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while (intel_breadcrumbs_busy(engine))
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cond_resched();
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}
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/* Finally reset hw state */
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tl->seqno = seqno;
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intel_engine_init_global_seqno(engine, seqno);
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}
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list_for_each_entry(timeline, &i915->gt.timelines, link) {
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for_each_engine(engine, i915, id) {
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struct intel_timeline *tl = &timeline->engine[id];
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memset(tl->sync_seqno, 0, sizeof(tl->sync_seqno));
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}
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}
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return 0;
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}
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int i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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lockdep_assert_held(&dev_priv->drm.struct_mutex);
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if (seqno == 0)
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return -EINVAL;
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/* HWS page needs to be set less than what we
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* will inject to ring
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*/
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return reset_all_global_seqno(dev_priv, seqno - 1);
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}
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static int reserve_seqno(struct intel_engine_cs *engine)
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{
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u32 active = ++engine->timeline->inflight_seqnos;
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u32 seqno = engine->timeline->seqno;
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int ret;
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/* Reservation is fine until we need to wrap around */
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if (likely(!add_overflows(seqno, active)))
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return 0;
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/* Even though we are tracking inflight seqno individually on each
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* engine, other engines may be observing us using hw semaphores and
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* so we need to idle all engines before wrapping around this engine.
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* As all engines are then idle, we can reset the seqno on all, so
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* we don't stall in quick succession if each engine is being
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* similarly utilized.
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*/
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ret = reset_all_global_seqno(engine->i915, 0);
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if (ret) {
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engine->timeline->inflight_seqnos--;
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return ret;
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}
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return 0;
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}
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static u32 timeline_get_seqno(struct intel_timeline *tl)
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{
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return ++tl->seqno;
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