drm/amdgpu: Register MCE notifier for Aldebaran RAS
On Aldebaran, GPU driver will handle bad page retirement for GPU memory even though UMC is host managed. As a result, register a bad page retirement handler on the mce notifier chain to retire bad pages on Aldebaran. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Mukul Joshi
Alex Deucher
parent
f38ce910d8
commit
12b2cab790
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@ -35,7 +35,11 @@
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#include "amdgpu_xgmi.h"
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#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
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#include "atom.h"
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#ifdef CONFIG_X86_MCE_AMD
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#include <asm/mce.h>
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static bool notifier_registered;
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#endif
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static const char *RAS_FS_NAME = "ras";
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const char *ras_error_string[] = {
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@ -107,6 +111,9 @@ static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con,
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uint64_t addr);
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static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev,
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uint64_t addr);
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#ifdef CONFIG_X86_MCE_AMD
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static void amdgpu_register_bad_pages_mca_notifier(void);
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#endif
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void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
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{
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@ -2098,6 +2105,11 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev)
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adev->smu.ppt_funcs->send_hbm_bad_pages_num(&adev->smu, con->eeprom_control.ras_num_recs);
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}
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#ifdef CONFIG_X86_MCE_AMD
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if ((adev->asic_type == CHIP_ALDEBARAN) &&
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(adev->gmc.xgmi.connected_to_cpu))
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amdgpu_register_bad_pages_mca_notifier();
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#endif
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return 0;
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free:
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@ -2589,3 +2601,132 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev)
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kfree(con);
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}
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}
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#ifdef CONFIG_X86_MCE_AMD
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static struct amdgpu_device *find_adev(uint32_t node_id)
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{
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struct amdgpu_gpu_instance *gpu_instance;
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int i;
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struct amdgpu_device *adev = NULL;
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mutex_lock(&mgpu_info.mutex);
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for (i = 0; i < mgpu_info.num_gpu; i++) {
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gpu_instance = &(mgpu_info.gpu_ins[i]);
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adev = gpu_instance->adev;
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if (adev->gmc.xgmi.connected_to_cpu &&
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adev->gmc.xgmi.physical_node_id == node_id)
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break;
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adev = NULL;
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}
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mutex_unlock(&mgpu_info.mutex);
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return adev;
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}
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#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF)
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#define GET_UMC_INST(m) (((m) >> 21) & 0x7)
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#define GET_CHAN_INDEX(m) ((((m) >> 12) & 0x3) | (((m) >> 18) & 0x4))
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#define GPU_ID_OFFSET 8
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static int amdgpu_bad_page_notifier(struct notifier_block *nb,
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unsigned long val, void *data)
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{
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struct mce *m = (struct mce *)data;
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struct amdgpu_device *adev = NULL;
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uint32_t gpu_id = 0;
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uint32_t umc_inst = 0;
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uint32_t ch_inst, channel_index = 0;
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struct ras_err_data err_data = {0, 0, 0, NULL};
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struct eeprom_table_record err_rec;
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uint64_t retired_page;
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/*
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* If the error was generated in UMC_V2, which belongs to GPU UMCs,
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* and error occurred in DramECC (Extended error code = 0) then only
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* process the error, else bail out.
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*/
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if (!m || !((smca_get_bank_type(m->bank) == SMCA_UMC_V2) &&
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(XEC(m->status, 0x3f) == 0x0)))
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return NOTIFY_DONE;
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/*
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* If it is correctable error, return.
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*/
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if (mce_is_correctable(m))
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return NOTIFY_OK;
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/*
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* GPU Id is offset by GPU_ID_OFFSET in MCA_IPID_UMC register.
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*/
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gpu_id = GET_MCA_IPID_GPUID(m->ipid) - GPU_ID_OFFSET;
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adev = find_adev(gpu_id);
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if (!adev) {
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DRM_WARN("%s: Unable to find adev for gpu_id: %d\n", __func__,
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gpu_id);
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return NOTIFY_DONE;
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}
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/*
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* If it is uncorrectable error, then find out UMC instance and
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* channel index.
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*/
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umc_inst = GET_UMC_INST(m->ipid);
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ch_inst = GET_CHAN_INDEX(m->ipid);
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dev_info(adev->dev, "Uncorrectable error detected in UMC inst: %d, chan_idx: %d",
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umc_inst, ch_inst);
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memset(&err_rec, 0x0, sizeof(struct eeprom_table_record));
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/*
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* Translate UMC channel address to Physical address
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*/
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channel_index =
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adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num
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+ ch_inst];
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retired_page = ADDR_OF_8KB_BLOCK(m->addr) |
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ADDR_OF_256B_BLOCK(channel_index) |
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OFFSET_IN_256B_BLOCK(m->addr);
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err_rec.address = m->addr;
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err_rec.retired_page = retired_page >> AMDGPU_GPU_PAGE_SHIFT;
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err_rec.ts = (uint64_t)ktime_get_real_seconds();
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err_rec.err_type = AMDGPU_RAS_EEPROM_ERR_NON_RECOVERABLE;
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err_rec.cu = 0;
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err_rec.mem_channel = channel_index;
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err_rec.mcumc_id = umc_inst;
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err_data.err_addr = &err_rec;
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err_data.err_addr_cnt = 1;
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if (amdgpu_bad_page_threshold != 0) {
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amdgpu_ras_add_bad_pages(adev, err_data.err_addr,
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err_data.err_addr_cnt);
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amdgpu_ras_save_bad_pages(adev);
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}
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return NOTIFY_OK;
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}
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static struct notifier_block amdgpu_bad_page_nb = {
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.notifier_call = amdgpu_bad_page_notifier,
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.priority = MCE_PRIO_UC,
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};
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static void amdgpu_register_bad_pages_mca_notifier(void)
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{
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/*
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* Register the x86 notifier only once
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* with MCE subsystem.
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*/
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if (notifier_registered == false) {
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mce_register_decode_chain(&amdgpu_bad_page_nb);
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notifier_registered = true;
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}
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}
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#endif
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