arch/tile: tilegx PCI root complex support
This change implements PCIe root complex support for tilegx using the kernel support layer for accessing the TRIO hardware shim. Reviewed-by: Bjorn Helgaas <bhelgaas@google.com> [changes in 07487f3] Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
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Chris Metcalf
parent
bce5bbbb23
commit
129622672d
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@ -356,6 +356,9 @@ config PCI
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default y
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select PCI_DOMAINS
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select GENERIC_PCI_IOMAP
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select TILE_GXIO_TRIO if TILEGX
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select ARCH_SUPPORTS_MSI if TILEGX
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select PCI_MSI if TILEGX
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---help---
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Enable PCI root complex support, so PCIe endpoint devices can
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be attached to the Tile chip. Many, but not all, PCI devices
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@ -16,8 +16,11 @@
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#define _ASM_TILE_PCI_H
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#include <linux/pci.h>
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#include <linux/numa.h>
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#include <asm-generic/pci_iomap.h>
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#ifndef __tilegx__
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/*
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* Structure of a PCI controller (host bridge)
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*/
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@ -40,6 +43,91 @@ struct pci_controller {
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struct resource mem_resources[3];
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};
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/*
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* This flag tells if the platform is TILEmpower that needs
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* special configuration for the PLX switch chip.
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*/
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extern int tile_plx_gen1;
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static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
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#define TILE_NUM_PCIE 2
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#else
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#include <asm/page.h>
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#include <gxio/trio.h>
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/**
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* We reserve the hugepage-size address range at the top of the 64-bit address
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* space to serve as the PCI window, emulating the BAR0 space of an endpoint
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* device. This window is used by the chip-to-chip applications running on
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* the RC node. The reason for carving out this window is that Mem-Maps that
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* back up this window will not overlap with those that map the real physical
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* memory.
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*/
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#define PCIE_HOST_BAR0_SIZE HPAGE_SIZE
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#define PCIE_HOST_BAR0_START HPAGE_MASK
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/**
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* The first PAGE_SIZE of the above "BAR" window is mapped to the
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* gxpci_host_regs structure.
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*/
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#define PCIE_HOST_REGS_SIZE PAGE_SIZE
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/*
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* This is the PCI address where the Mem-Map interrupt regions start.
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* We use the 2nd to the last huge page of the 64-bit address space.
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* The last huge page is used for the rootcomplex "bar", for C2C purpose.
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*/
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#define MEM_MAP_INTR_REGIONS_BASE (HPAGE_MASK - HPAGE_SIZE)
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/*
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* Each Mem-Map interrupt region occupies 4KB.
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*/
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#define MEM_MAP_INTR_REGION_SIZE (1<< TRIO_MAP_MEM_LIM__ADDR_SHIFT)
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/*
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* Structure of a PCI controller (host bridge) on Gx.
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*/
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struct pci_controller {
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/* Pointer back to the TRIO that this PCIe port is connected to. */
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gxio_trio_context_t *trio;
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int mac; /* PCIe mac index on the TRIO shim */
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int trio_index; /* Index of TRIO shim that contains the MAC. */
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int pio_mem_index; /* PIO region index for memory access */
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/*
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* Mem-Map regions for all the memory controllers so that Linux can
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* map all of its physical memory space to the PCI bus.
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*/
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int mem_maps[MAX_NUMNODES];
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int index; /* PCI domain number */
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struct pci_bus *root_bus;
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int last_busno;
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struct pci_ops *ops;
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/* Table that maps the INTx numbers to Linux irq numbers. */
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int irq_intx_table[4];
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struct resource mem_space;
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/* Address ranges that are routed to this controller/bridge. */
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struct resource mem_resources[3];
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};
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extern struct pci_controller pci_controllers[TILEGX_NUM_TRIO * TILEGX_TRIO_PCIES];
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extern gxio_trio_context_t trio_contexts[TILEGX_NUM_TRIO];
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extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
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#endif /* __tilegx__ */
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/*
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* The hypervisor maps the entirety of CPA-space as bus addresses, so
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* bus addresses are physical addresses. The networking and block
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@ -50,12 +138,8 @@ struct pci_controller {
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int __init tile_pci_init(void);
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int __init pcibios_init(void);
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static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
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void __devinit pcibios_fixup_bus(struct pci_bus *bus);
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#define TILE_NUM_PCIE 2
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#define pci_domain_nr(bus) (((struct pci_controller *)(bus)->sysdata)->index)
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/*
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@ -79,12 +163,6 @@ static inline int pcibios_assign_all_busses(void)
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#define PCIBIOS_MIN_MEM 0
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#define PCIBIOS_MIN_IO 0
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/*
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* This flag tells if the platform is TILEmpower that needs
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* special configuration for the PLX switch chip.
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*/
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extern int tile_plx_gen1;
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/* Use any cpu for PCI. */
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#define cpumask_of_pcibus(bus) cpu_online_mask
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@ -14,4 +14,8 @@ obj-$(CONFIG_SMP) += smpboot.o smp.o tlb.o
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obj-$(CONFIG_MODULES) += module.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel_$(BITS).o
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ifdef CONFIG_TILEGX
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obj-$(CONFIG_PCI) += pci_gx.o
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else
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obj-$(CONFIG_PCI) += pci.o
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endif
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File diff suppressed because it is too large
Load Diff
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@ -1344,6 +1344,7 @@ void __init setup_arch(char **cmdline_p)
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#ifdef CONFIG_PCI
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#if !defined (__tilegx__)
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/*
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* Initialize the PCI structures. This is done before memory
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* setup so that we know whether or not a pci_reserve region
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@ -1351,6 +1352,7 @@ void __init setup_arch(char **cmdline_p)
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*/
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if (tile_pci_init() == 0)
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pci_reserve_mb = 0;
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#endif
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/* PCI systems reserve a region just below 4GB for mapping iomem. */
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pci_reserve_end_pfn = (1 << (32 - PAGE_SHIFT));
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@ -1379,6 +1381,10 @@ void __init setup_arch(char **cmdline_p)
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setup_cpu(1);
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setup_clock();
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load_hv_initrd();
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#if defined(CONFIG_PCI) && defined (__tilegx__)
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tile_pci_init();
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#endif
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}
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@ -575,13 +575,6 @@ void __iomem *ioremap_prot(resource_size_t phys_addr, unsigned long size,
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}
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EXPORT_SYMBOL(ioremap_prot);
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/* Map a PCI MMIO bus address into VA space. */
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void __iomem *ioremap(resource_size_t phys_addr, unsigned long size)
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{
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panic("ioremap for PCI MMIO is not supported");
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}
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EXPORT_SYMBOL(ioremap);
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/* Unmap an MMIO VA mapping. */
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void iounmap(volatile void __iomem *addr_in)
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{
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@ -2143,9 +2143,9 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
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quirk_unhide_mch_dev6);
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#ifdef CONFIG_TILE
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#ifdef CONFIG_TILEPRO
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/*
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* The Tilera TILEmpower platform needs to set the link speed
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* The Tilera TILEmpower tilepro platform needs to set the link speed
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* to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
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* setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
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* capability register of the PEX8624 PCIe switch. The switch
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@ -2160,7 +2160,7 @@ static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
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}
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}
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DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
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#endif /* CONFIG_TILE */
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#endif /* CONFIG_TILEPRO */
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#ifdef CONFIG_PCI_MSI
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/* Some chipsets do not support MSI. We cannot easily rely on setting
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