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OpenCloudOS-Kernel
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imx31: define and use MX31_IO_ADDRESS 

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Daniel Mack <daniel@caiaq.de>
Cc: Greg Kroah-Hartman <gregkh@suse.de>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Magnus Lilja <lilja.magnus@gmail.com>
This commit is contained in:
Uwe Kleine-König 2009-12-16 19:06:12 +01:00
parent bc9ea6c7f5
commit 1273e7686f
6 changed files with 14 additions and 6 deletions
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3
arch/arm/mach-mx3/clock-imx31.c
View File

@ -625,7 +625,8 @@ int __init mx31_clocks_init(unsigned long fref)
__raw_writel(reg, MXC_CCM_PMCR1);
}
mxc_timer_init(&ipg_clk, IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
MX31_INT_GPT);
return 0;
}

2
arch/arm/mach-mx3/crm_regs.h
View File

@ -24,7 +24,7 @@
#define CKIH_CLK_FREQ_27MHZ 27000000
#define CKIL_CLK_FREQ 32768
#define MXC_CCM_BASE IO_ADDRESS(MX31_CCM_BASE_ADDR)
#define MXC_CCM_BASE MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR)
/* Register addresses */
#define MXC_CCM_CCMR (MXC_CCM_BASE + 0x00)

2
arch/arm/mach-mx3/iomux-imx31.c
View File

@ -29,7 +29,7 @@
/*
* IOMUX register (base) addresses
*/
#define IOMUX_BASE IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
#define IOMUXGPR (IOMUX_BASE + 0x008)

4
arch/arm/plat-mxc/ehci.c
View File

@ -43,7 +43,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
unsigned int v;
if (cpu_is_mx31()) {
v = readl(IO_ADDRESS(MX31_OTG_BASE_ADDR +
v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
switch (port) {
@ -79,7 +79,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
break;
}
writel(v, IO_ADDRESS(MX31_OTG_BASE_ADDR +
writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR +
USBCTRL_OTGBASE_OFFSET));
return 0;
}

2
arch/arm/plat-mxc/include/mach/board-mx31ads.h
View File

@ -14,7 +14,7 @@
#include <mach/hardware.h>
/* Base address of PBC controller */
#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
#define PBC_BASE_ADDRESS MX31_CS4_BASE_ADDR_VIRT
/* Offsets for the PBC Controller register */
/* PBC Board status register offset */

7
arch/arm/plat-mxc/include/mach/mx31.h
View File

@ -109,6 +109,13 @@
#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
#define MX31_IO_ADDRESS(x) ( \
IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \
IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
IMX_IO_ADDRESS(x, MX31_SPBA0))
#define MX31_INT_I2C3 3
#define MX31_INT_I2C2 4
#define MX31_INT_MPEG4_ENCODER 5