drm/amd/display: fix opp header register define
Signed-off-by: Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by: Eric Bernstein <Eric.Bernstein@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -46,6 +46,16 @@
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#define OPP_REG_LIST_DCN10(id) \
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#define OPP_REG_LIST_DCN10(id) \
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OPP_REG_LIST_DCN(id)
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OPP_REG_LIST_DCN(id)
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#define OPP_COMMON_REG_VARIABLE_LIST \
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uint32_t FMT_BIT_DEPTH_CONTROL; \
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uint32_t FMT_CONTROL; \
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uint32_t FMT_DITHER_RAND_R_SEED; \
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uint32_t FMT_DITHER_RAND_G_SEED; \
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uint32_t FMT_DITHER_RAND_B_SEED; \
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uint32_t FMT_CLAMP_CNTL; \
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uint32_t FMT_DYNAMIC_EXP_CNTL; \
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uint32_t FMT_MAP420_MEMORY_CONTROL;
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#define OPP_MASK_SH_LIST_DCN(mask_sh) \
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#define OPP_MASK_SH_LIST_DCN(mask_sh) \
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OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
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OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \
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OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
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OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \
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@ -97,6 +107,10 @@
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type FMT_MAP420MEM_PWR_FORCE; \
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type FMT_MAP420MEM_PWR_FORCE; \
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type FMT_STEREOSYNC_OVERRIDE;
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type FMT_STEREOSYNC_OVERRIDE;
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struct dcn10_opp_registers {
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OPP_COMMON_REG_VARIABLE_LIST
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};
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struct dcn10_opp_shift {
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struct dcn10_opp_shift {
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OPP_DCN10_REG_FIELD_LIST(uint8_t)
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OPP_DCN10_REG_FIELD_LIST(uint8_t)
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};
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};
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@ -105,17 +119,6 @@ struct dcn10_opp_mask {
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OPP_DCN10_REG_FIELD_LIST(uint32_t)
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OPP_DCN10_REG_FIELD_LIST(uint32_t)
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};
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};
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struct dcn10_opp_registers {
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uint32_t FMT_BIT_DEPTH_CONTROL;
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uint32_t FMT_CONTROL;
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uint32_t FMT_DITHER_RAND_R_SEED;
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uint32_t FMT_DITHER_RAND_G_SEED;
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uint32_t FMT_DITHER_RAND_B_SEED;
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uint32_t FMT_CLAMP_CNTL;
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uint32_t FMT_DYNAMIC_EXP_CNTL;
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uint32_t FMT_MAP420_MEMORY_CONTROL;
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};
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struct dcn10_opp {
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struct dcn10_opp {
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struct output_pixel_processor base;
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struct output_pixel_processor base;
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