drm/amdgpu: make software ring functions reuseable for newer VCN
Software ring will be supported only from VCN4 Signed-off-by: Leo Liu <leo.liu@amd.com> Reviewed-by: James Zhu <James.Zhu@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1728,7 +1728,7 @@ static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
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}
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}
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}
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}
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static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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u64 seq, uint32_t flags)
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u64 seq, uint32_t flags)
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{
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{
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WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
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WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
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@ -1740,15 +1740,13 @@ static void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_TRAP);
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}
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}
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static void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
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void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring)
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{
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{
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_END);
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}
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}
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static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring,
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void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
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struct amdgpu_job *job,
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struct amdgpu_ib *ib, uint32_t flags)
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struct amdgpu_ib *ib,
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uint32_t flags)
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{
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{
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uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
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uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
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@ -1759,7 +1757,7 @@ static void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, ib->length_dw);
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amdgpu_ring_write(ring, ib->length_dw);
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}
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}
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static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask)
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uint32_t val, uint32_t mask)
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{
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{
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WAIT);
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@ -1768,7 +1766,7 @@ static void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_
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amdgpu_ring_write(ring, val);
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amdgpu_ring_write(ring, val);
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}
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}
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static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
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void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
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uint32_t vmid, uint64_t pd_addr)
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uint32_t vmid, uint64_t pd_addr)
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{
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{
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
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@ -1783,7 +1781,8 @@ static void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
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vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
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vcn_v3_0_dec_sw_ring_emit_reg_wait(ring, data0, data1, mask);
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}
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}
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static void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
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void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val)
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{
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{
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
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amdgpu_ring_write(ring, VCN_DEC_SW_CMD_REG_WRITE);
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amdgpu_ring_write(ring, reg << 2);
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amdgpu_ring_write(ring, reg << 2);
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@ -26,4 +26,16 @@
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extern const struct amdgpu_ip_block_version vcn_v3_0_ip_block;
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extern const struct amdgpu_ip_block_version vcn_v3_0_ip_block;
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void vcn_v3_0_dec_sw_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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u64 seq, uint32_t flags);
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void vcn_v3_0_dec_sw_ring_insert_end(struct amdgpu_ring *ring);
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void vcn_v3_0_dec_sw_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job,
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struct amdgpu_ib *ib, uint32_t flags);
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void vcn_v3_0_dec_sw_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val, uint32_t mask);
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void vcn_v3_0_dec_sw_ring_emit_vm_flush(struct amdgpu_ring *ring,
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uint32_t vmid, uint64_t pd_addr);
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void vcn_v3_0_dec_sw_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
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uint32_t val);
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#endif /* __VCN_V3_0_H__ */
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#endif /* __VCN_V3_0_H__ */
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