Samsung 3rd DT updates for v3.20
- add DISP1 power domain for support HDMI support on exynos5420/5422/5800 and the power domain node including FIMD1, MIXER and HDMI modules (tested on exynos5420 Peach Pit and exynos5800 Peach Pi Chromebooks and exynos5422 Odroid XU3 by Javier Martinez Canillas) Note this is including a patch for adding clock IDs for the DISP1 power domain with Mike and Sylwester's acks so that could be handled together to avoid non-working. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJUyXrPAAoJEA0Cl+kVi2xqxRgP/3+NBTV3qWQ6+pYTl4kCebIz 6lCmjgMeLZFfqRT420ouK1w7K0ra2eeeLX1GNZHOayzzBfFEJfR7GL6GMh40NqHy qs5CtAGTDlwb8ZSIECBcklABXICE6nujl9lqa3WD1vjwJy9Zug/3BUYfSlxwJap6 Uzrw1tGt+k7WcHWWSyC8FCsK8gpvxb5cAIcBYTRPrxwHcGGeVfvn4IFBcz5eYMsz EttmkxXOVcpVJ90c+iSyrLSVuc+YH0m+ITrYj0/EjlzJzlQQ1NKjBg+eUnWU9Zef L7bZp3r4ZWU1FYNzQuuUXaEwSfSzGJ2icKLmX5nmcH5XPSBWPTYRDEIJe2fX7j+X 1zhxi992LvZysIgJrfPJf8N6vsOeKc2mfz/65YLjcbSpFX7Qe5hISlMIRAWYT/69 IqVsH0E05VvXtpFKfSlfapsztAmfVsaRZwsHhvmMEZdzUatJehQAn2t5gftZQ0iu 9/z1HD3uszZWPghbRuFBalmgWB8WEhF8yhiIRBx1o/ML7DAcdLtrZ2HrSobjnBYz APnxZAU6s4QwAAk5bQCN7p3jPqSnZUakg1ETeXf3j1qvfWhTmKcYPggYDtfb2Nou tIwJdY3VAJWC+9n/4pKw5OKsCdE/34DUdT9rkuIBhO+AbRpeGkztSVJmBRU4bGQM 1yVwptBrUybxDLqM4Lad =9Imn -----END PGP SIGNATURE----- Merge tag 'samsung-dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt Merge "Samsung 3rd DT updates for v3.20" from Kukjin Kim: - add DISP1 power domain for support HDMI support on exynos5420/5422/5800 and the power domain node including FIMD1, MIXER and HDMI modules (tested on exynos5420 Peach Pit and exynos5800 Peach Pi Chromebooks and exynos5422 Odroid XU3 by Javier Martinez Canillas) Note this is including a patch for adding clock IDs for the DISP1 power domain with Mike and Sylwester's acks so that could be handled together to avoid non-working. * tag 'samsung-dt-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: dts: Add DISP1 power domain for exynos5420 clk: exynos5420: Add IDs for clocks used in DISP1 power domain Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
1215c3e65a
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@ -274,6 +274,20 @@
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#power-domain-cells = <0>;
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};
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disp_pd: power-domain@100440C0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440C0 0x20>;
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#power-domain-cells = <0>;
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MOUT_SW_ACLK200>,
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<&clock CLK_MOUT_USER_ACLK200_DISP1>,
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<&clock CLK_MOUT_SW_ACLK300>,
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<&clock CLK_MOUT_USER_ACLK300_DISP1>,
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<&clock CLK_MOUT_SW_ACLK400>,
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<&clock CLK_MOUT_USER_ACLK400_DISP1>;
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clock-names = "oscclk", "pclk0", "clk0",
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"pclk1", "clk1", "pclk2", "clk2";
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};
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pinctrl_0: pinctrl@13400000 {
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compatible = "samsung,exynos5420-pinctrl";
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reg = <0x13400000 0x1000>;
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@ -541,6 +555,7 @@
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fimd: fimd@14400000 {
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clocks = <&clock CLK_SCLK_FIMD1>, <&clock CLK_FIMD1>;
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clock-names = "sclk_fimd", "fimd";
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power-domains = <&disp_pd>;
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};
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adc: adc@12D10000 {
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@ -714,6 +729,7 @@
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phy = <&hdmiphy>;
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samsung,syscon-phandle = <&pmu_system_controller>;
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status = "disabled";
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power-domains = <&disp_pd>;
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};
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hdmiphy: hdmiphy@145D0000 {
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@ -726,6 +742,7 @@
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interrupts = <0 94 0>;
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clocks = <&clock CLK_MIXER>, <&clock CLK_SCLK_HDMI>;
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clock-names = "mixer", "sclk_hdmi";
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power-domains = <&disp_pd>;
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};
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gsc_0: video-scaler@13e00000 {
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@ -635,8 +635,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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SRC_TOP3, 0, 1),
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MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
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SRC_TOP3, 4, 1),
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MUX(0, "mout_user_aclk200_disp1", mout_user_aclk200_disp1_p,
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SRC_TOP3, 8, 1),
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MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
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mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
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MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
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SRC_TOP3, 12, 1),
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MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
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@ -663,8 +663,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
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SRC_TOP4, 28, 1),
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MUX(0, "mout_user_aclk400_disp1", mout_user_aclk400_disp1_p,
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SRC_TOP5, 0, 1),
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MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
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mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
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MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
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SRC_TOP5, 4, 1),
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MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
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@ -675,8 +675,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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SRC_TOP5, 16, 1),
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MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
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SRC_TOP5, 20, 1),
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MUX(0, "mout_user_aclk300_disp1", mout_user_aclk300_disp1_p,
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SRC_TOP5, 24, 1),
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MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
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mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
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MUX(0, "mout_user_aclk300_gscl", mout_user_aclk300_gscl_p,
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SRC_TOP5, 28, 1),
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@ -693,7 +693,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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SRC_TOP10, 0, 1),
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MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
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SRC_TOP10, 4, 1),
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MUX(0, "mout_sw_aclk200", mout_sw_aclk200_p, SRC_TOP10, 8, 1),
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MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
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SRC_TOP10, 8, 1),
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MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
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SRC_TOP10, 12, 1),
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MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
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@ -717,8 +718,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
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SRC_TOP11, 28, 1),
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MUX(0, "mout_sw_aclk400_disp1", mout_sw_aclk400_disp1_p,
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SRC_TOP12, 4, 1),
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MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
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mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
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MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
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SRC_TOP12, 8, 1),
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MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
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@ -726,8 +727,8 @@ static struct samsung_mux_clock exynos5x_mux_clks[] __initdata = {
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MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
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MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
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SRC_TOP12, 20, 1),
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MUX(0, "mout_sw_aclk300_disp1", mout_sw_aclk300_disp1_p,
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SRC_TOP12, 24, 1),
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MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
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mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
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MUX(0, "mout_sw_aclk300_gscl", mout_sw_aclk300_gscl_p,
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SRC_TOP12, 28, 1),
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@ -204,6 +204,12 @@
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#define CLK_MOUT_MAUDIO0 643
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#define CLK_MOUT_USER_ACLK333 644
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#define CLK_MOUT_SW_ACLK333 645
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#define CLK_MOUT_USER_ACLK200_DISP1 646
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#define CLK_MOUT_SW_ACLK200 647
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#define CLK_MOUT_USER_ACLK300_DISP1 648
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#define CLK_MOUT_SW_ACLK300 649
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#define CLK_MOUT_USER_ACLK400_DISP1 650
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#define CLK_MOUT_SW_ACLK400 651
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/* divider clocks */
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#define CLK_DOUT_PIXEL 768
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