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clk: ingenic: Fix divider calculation with div tables 

The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.

Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.

Fixes: a9fa2893fc ("clk: ingenic: Add support for divider tables")
Cc: <stable@vger.kernel.org> # 5.2
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lore.kernel.org/r/20201212135733.38050-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Paul Cercueil 2020-12-12 13:57:33 +00:00 committed by Stephen Boyd
parent 3650b228f8
commit 11a163f2c7
1 changed files with 10 additions and 4 deletions
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14
drivers/clk/ingenic/cgu.c
View File

@ -392,15 +392,21 @@ static unsigned int
ingenic_clk_calc_hw_div(const struct ingenic_cgu_clk_info *clk_info,
unsigned int div)
{
unsigned int i;
unsigned int i, best_i = 0, best = (unsigned int)-1;
for (i = 0; i < (1 << clk_info->div.bits)
&& clk_info->div.div_table[i]; i++) {
if (clk_info->div.div_table[i] >= div)
return i;
if (clk_info->div.div_table[i] >= div &&
clk_info->div.div_table[i] < best) {
best = clk_info->div.div_table[i];
best_i = i;
if (div == best)
break;
}
}
return i - 1;
return best_i;
}
static unsigned