iommu/io-pgtable-arm-v7s: Support lockless operation
Mirroring the LPAE implementation, rework the v7s code to be robust against concurrent operations. The same two potential races exist, and are solved in the same manner, with the fixed 2-level structure making life ever so slightly simpler. What complicates matters compared to LPAE, however, is large page entries, since we can't update a block of 16 PTEs atomically, nor assume available software bits to do clever things with. As most users are never likely to do partial unmaps anyway (due to DMA API rules), it doesn't seem unreasonable for this case to remain behind a serialising lock; we just pull said lock down into the bowels of the implementation so it's well out of the way of the normal call paths. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Robin Murphy
Will Deacon
parent
2c3d273eab
commit
119ff305b0
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@ -32,6 +32,7 @@
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#define pr_fmt(fmt) "arm-v7s io-pgtable: " fmt
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#include <linux/atomic.h>
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#include <linux/dma-mapping.h>
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#include <linux/gfp.h>
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#include <linux/iommu.h>
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@ -39,6 +40,7 @@
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#include <linux/kmemleak.h>
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#include <linux/sizes.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <asm/barrier.h>
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@ -168,6 +170,7 @@ struct arm_v7s_io_pgtable {
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arm_v7s_iopte *pgd;
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struct kmem_cache *l2_tables;
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spinlock_t split_lock;
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};
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static dma_addr_t __arm_v7s_dma_addr(void *pages)
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@ -396,16 +399,22 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
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static arm_v7s_iopte arm_v7s_install_table(arm_v7s_iopte *table,
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arm_v7s_iopte *ptep,
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arm_v7s_iopte curr,
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struct io_pgtable_cfg *cfg)
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{
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arm_v7s_iopte new;
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arm_v7s_iopte old, new;
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new = virt_to_phys(table) | ARM_V7S_PTE_TYPE_TABLE;
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if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS)
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new |= ARM_V7S_ATTR_NS_TABLE;
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__arm_v7s_set_pte(ptep, new, 1, cfg);
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return new;
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/* Ensure the table itself is visible before its PTE can be */
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wmb();
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old = cmpxchg_relaxed(ptep, curr, new);
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__arm_v7s_pte_sync(ptep, 1, cfg);
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return old;
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}
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static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
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@ -429,16 +438,23 @@ static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
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return -EINVAL;
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/* Grab a pointer to the next level */
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pte = *ptep;
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pte = READ_ONCE(*ptep);
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if (!pte) {
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cptep = __arm_v7s_alloc_table(lvl + 1, GFP_ATOMIC, data);
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if (!cptep)
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return -ENOMEM;
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arm_v7s_install_table(cptep, ptep, cfg);
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} else if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) {
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cptep = iopte_deref(pte, lvl);
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pte = arm_v7s_install_table(cptep, ptep, 0, cfg);
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if (pte)
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__arm_v7s_free_table(cptep, lvl + 1, data);
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} else {
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/* We've no easy way of knowing if it's synced yet, so... */
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__arm_v7s_pte_sync(ptep, 1, cfg);
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}
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if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) {
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cptep = iopte_deref(pte, lvl);
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} else if (pte) {
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/* We require an unmap first */
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WARN_ON(!selftest_running);
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return -EEXIST;
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@ -491,27 +507,31 @@ static void arm_v7s_free_pgtable(struct io_pgtable *iop)
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kfree(data);
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}
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static void arm_v7s_split_cont(struct arm_v7s_io_pgtable *data,
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unsigned long iova, int idx, int lvl,
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arm_v7s_iopte *ptep)
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static arm_v7s_iopte arm_v7s_split_cont(struct arm_v7s_io_pgtable *data,
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unsigned long iova, int idx, int lvl,
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arm_v7s_iopte *ptep)
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{
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struct io_pgtable *iop = &data->iop;
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arm_v7s_iopte pte;
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size_t size = ARM_V7S_BLOCK_SIZE(lvl);
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int i;
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/* Check that we didn't lose a race to get the lock */
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pte = *ptep;
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if (!arm_v7s_pte_is_cont(pte, lvl))
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return pte;
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ptep -= idx & (ARM_V7S_CONT_PAGES - 1);
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pte = arm_v7s_cont_to_pte(*ptep, lvl);
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for (i = 0; i < ARM_V7S_CONT_PAGES; i++) {
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ptep[i] = pte;
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pte += size;
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}
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pte = arm_v7s_cont_to_pte(pte, lvl);
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for (i = 0; i < ARM_V7S_CONT_PAGES; i++)
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ptep[i] = pte + i * size;
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__arm_v7s_pte_sync(ptep, ARM_V7S_CONT_PAGES, &iop->cfg);
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size *= ARM_V7S_CONT_PAGES;
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io_pgtable_tlb_add_flush(iop, iova, size, size, true);
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io_pgtable_tlb_sync(iop);
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return pte;
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}
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static int arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
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@ -542,7 +562,16 @@ static int arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
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__arm_v7s_set_pte(&tablep[i], pte, num_entries, cfg);
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}
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arm_v7s_install_table(tablep, ptep, cfg);
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pte = arm_v7s_install_table(tablep, ptep, blk_pte, cfg);
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if (pte != blk_pte) {
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__arm_v7s_free_table(tablep, 2, data);
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if (!ARM_V7S_PTE_IS_TABLE(pte, 1))
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return 0;
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tablep = iopte_deref(pte, 1);
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return __arm_v7s_unmap(data, iova, size, 2, tablep);
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}
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io_pgtable_tlb_add_flush(&data->iop, iova, size, size, true);
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return size;
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@ -563,17 +592,28 @@ static int __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
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idx = ARM_V7S_LVL_IDX(iova, lvl);
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ptep += idx;
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do {
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if (WARN_ON(!ARM_V7S_PTE_IS_VALID(ptep[i])))
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pte[i] = READ_ONCE(ptep[i]);
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if (WARN_ON(!ARM_V7S_PTE_IS_VALID(pte[i])))
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return 0;
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pte[i] = ptep[i];
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} while (++i < num_entries);
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/*
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* If we've hit a contiguous 'large page' entry at this level, it
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* needs splitting first, unless we're unmapping the whole lot.
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*
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* For splitting, we can't rewrite 16 PTEs atomically, and since we
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* can't necessarily assume TEX remap we don't have a software bit to
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* mark live entries being split. In practice (i.e. DMA API code), we
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* will never be splitting large pages anyway, so just wrap this edge
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* case in a lock for the sake of correctness and be done with it.
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*/
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if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl))
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arm_v7s_split_cont(data, iova, idx, lvl, ptep);
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if (num_entries <= 1 && arm_v7s_pte_is_cont(pte[0], lvl)) {
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unsigned long flags;
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spin_lock_irqsave(&data->split_lock, flags);
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pte[0] = arm_v7s_split_cont(data, iova, idx, lvl, ptep);
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spin_unlock_irqrestore(&data->split_lock, flags);
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}
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/* If the size matches this level, we're in the right place */
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if (num_entries) {
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@ -631,7 +671,8 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
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u32 mask;
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do {
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pte = ptep[ARM_V7S_LVL_IDX(iova, ++lvl)];
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ptep += ARM_V7S_LVL_IDX(iova, ++lvl);
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pte = READ_ONCE(*ptep);
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ptep = iopte_deref(pte, lvl);
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} while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
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@ -672,6 +713,7 @@ static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
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if (!data)
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return NULL;
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spin_lock_init(&data->split_lock);
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data->l2_tables = kmem_cache_create("io-pgtable_armv7s_l2",
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ARM_V7S_TABLE_SIZE(2),
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ARM_V7S_TABLE_SIZE(2),
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