net: hns3: Add input key and action config support for flow director
Each flow director rule consists of input key and action. The input key is the condition for matching, includes tuples of L2/L3/L4 header. Action is the behaviour when a packet matches with the input key, such as drop the packet, or forward to a specified queue. The input key is stored in the tcam blocks, Each bit of input key can be masked. Signed-off-by: Jian Shen <shenjian15@huawei.com> Signed-off-by: Peng Li <lipeng321@huawei.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jian Shen
David S. Miller
parent
d695964d72
commit
1173286802
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@ -194,6 +194,8 @@ enum hclge_opcode_type {
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HCLGE_OPC_FD_MODE_CTRL = 0x1200,
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HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
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HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
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HCLGE_OPC_FD_TCAM_OP = 0x1203,
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HCLGE_OPC_FD_AD_OP = 0x1204,
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/* MDIO command */
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HCLGE_OPC_MDIO_CONFIG = 0x1900,
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@ -851,6 +853,49 @@ struct hclge_set_fd_key_config_cmd {
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u8 rsv2[8];
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};
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#define HCLGE_FD_EPORT_SW_EN_B 0
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struct hclge_fd_tcam_config_1_cmd {
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u8 stage;
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u8 xy_sel;
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u8 port_info;
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u8 rsv1[1];
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__le32 index;
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u8 entry_vld;
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u8 rsv2[7];
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u8 tcam_data[8];
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};
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struct hclge_fd_tcam_config_2_cmd {
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u8 tcam_data[24];
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};
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struct hclge_fd_tcam_config_3_cmd {
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u8 tcam_data[20];
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u8 rsv[4];
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};
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#define HCLGE_FD_AD_DROP_B 0
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#define HCLGE_FD_AD_DIRECT_QID_B 1
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#define HCLGE_FD_AD_QID_S 2
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#define HCLGE_FD_AD_QID_M GENMASK(12, 2)
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#define HCLGE_FD_AD_USE_COUNTER_B 12
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#define HCLGE_FD_AD_COUNTER_NUM_S 13
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#define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
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#define HCLGE_FD_AD_NXT_STEP_B 20
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#define HCLGE_FD_AD_NXT_KEY_S 21
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#define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21)
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#define HCLGE_FD_AD_WR_RULE_ID_B 0
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#define HCLGE_FD_AD_RULE_ID_S 1
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#define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1)
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struct hclge_fd_ad_config_cmd {
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u8 stage;
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u8 rsv1[3];
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__le32 index;
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__le64 ad_data;
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u8 rsv2[8];
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};
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int hclge_cmd_init(struct hclge_dev *hdev);
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static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
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{
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@ -3471,6 +3471,335 @@ static int hclge_init_fd_config(struct hclge_dev *hdev)
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return hclge_set_fd_key_config(hdev, HCLGE_FD_STAGE_1);
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}
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static int hclge_fd_tcam_config(struct hclge_dev *hdev, u8 stage, bool sel_x,
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int loc, u8 *key, bool is_add)
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{
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struct hclge_fd_tcam_config_1_cmd *req1;
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struct hclge_fd_tcam_config_2_cmd *req2;
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struct hclge_fd_tcam_config_3_cmd *req3;
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struct hclge_desc desc[3];
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int ret;
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hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_FD_TCAM_OP, false);
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desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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hclge_cmd_setup_basic_desc(&desc[1], HCLGE_OPC_FD_TCAM_OP, false);
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desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
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hclge_cmd_setup_basic_desc(&desc[2], HCLGE_OPC_FD_TCAM_OP, false);
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req1 = (struct hclge_fd_tcam_config_1_cmd *)desc[0].data;
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req2 = (struct hclge_fd_tcam_config_2_cmd *)desc[1].data;
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req3 = (struct hclge_fd_tcam_config_3_cmd *)desc[2].data;
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req1->stage = stage;
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req1->xy_sel = sel_x ? 1 : 0;
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hnae3_set_bit(req1->port_info, HCLGE_FD_EPORT_SW_EN_B, 0);
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req1->index = cpu_to_le32(loc);
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req1->entry_vld = sel_x ? is_add : 0;
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if (key) {
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memcpy(req1->tcam_data, &key[0], sizeof(req1->tcam_data));
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memcpy(req2->tcam_data, &key[sizeof(req1->tcam_data)],
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sizeof(req2->tcam_data));
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memcpy(req3->tcam_data, &key[sizeof(req1->tcam_data) +
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sizeof(req2->tcam_data)], sizeof(req3->tcam_data));
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}
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ret = hclge_cmd_send(&hdev->hw, desc, 3);
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if (ret)
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dev_err(&hdev->pdev->dev,
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"config tcam key fail, ret=%d\n",
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ret);
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return ret;
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}
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static int hclge_fd_ad_config(struct hclge_dev *hdev, u8 stage, int loc,
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struct hclge_fd_ad_data *action)
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{
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struct hclge_fd_ad_config_cmd *req;
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struct hclge_desc desc;
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u64 ad_data = 0;
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int ret;
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hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_FD_AD_OP, false);
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req = (struct hclge_fd_ad_config_cmd *)desc.data;
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req->index = cpu_to_le32(loc);
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req->stage = stage;
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hnae3_set_bit(ad_data, HCLGE_FD_AD_WR_RULE_ID_B,
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action->write_rule_id_to_bd);
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hnae3_set_field(ad_data, HCLGE_FD_AD_RULE_ID_M, HCLGE_FD_AD_RULE_ID_S,
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action->rule_id);
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ad_data <<= 32;
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hnae3_set_bit(ad_data, HCLGE_FD_AD_DROP_B, action->drop_packet);
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hnae3_set_bit(ad_data, HCLGE_FD_AD_DIRECT_QID_B,
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action->forward_to_direct_queue);
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hnae3_set_field(ad_data, HCLGE_FD_AD_QID_M, HCLGE_FD_AD_QID_S,
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action->queue_id);
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hnae3_set_bit(ad_data, HCLGE_FD_AD_USE_COUNTER_B, action->use_counter);
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hnae3_set_field(ad_data, HCLGE_FD_AD_COUNTER_NUM_M,
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HCLGE_FD_AD_COUNTER_NUM_S, action->counter_id);
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hnae3_set_bit(ad_data, HCLGE_FD_AD_NXT_STEP_B, action->use_next_stage);
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hnae3_set_field(ad_data, HCLGE_FD_AD_NXT_KEY_M, HCLGE_FD_AD_NXT_KEY_S,
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action->counter_id);
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req->ad_data = cpu_to_le64(ad_data);
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ret = hclge_cmd_send(&hdev->hw, &desc, 1);
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if (ret)
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dev_err(&hdev->pdev->dev, "fd ad config fail, ret=%d\n", ret);
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return ret;
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}
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static bool hclge_fd_convert_tuple(u32 tuple_bit, u8 *key_x, u8 *key_y,
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struct hclge_fd_rule *rule)
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{
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u16 tmp_x_s, tmp_y_s;
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u32 tmp_x_l, tmp_y_l;
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int i;
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if (rule->unused_tuple & tuple_bit)
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return true;
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switch (tuple_bit) {
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case 0:
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return false;
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case BIT(INNER_DST_MAC):
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for (i = 0; i < 6; i++) {
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calc_x(key_x[5 - i], rule->tuples.dst_mac[i],
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rule->tuples_mask.dst_mac[i]);
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calc_y(key_y[5 - i], rule->tuples.dst_mac[i],
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rule->tuples_mask.dst_mac[i]);
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}
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return true;
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case BIT(INNER_SRC_MAC):
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for (i = 0; i < 6; i++) {
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calc_x(key_x[5 - i], rule->tuples.src_mac[i],
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rule->tuples.src_mac[i]);
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calc_y(key_y[5 - i], rule->tuples.src_mac[i],
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rule->tuples.src_mac[i]);
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}
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return true;
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case BIT(INNER_VLAN_TAG_FST):
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calc_x(tmp_x_s, rule->tuples.vlan_tag1,
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rule->tuples_mask.vlan_tag1);
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calc_y(tmp_y_s, rule->tuples.vlan_tag1,
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rule->tuples_mask.vlan_tag1);
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*(__le16 *)key_x = cpu_to_le16(tmp_x_s);
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*(__le16 *)key_y = cpu_to_le16(tmp_y_s);
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return true;
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case BIT(INNER_ETH_TYPE):
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calc_x(tmp_x_s, rule->tuples.ether_proto,
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rule->tuples_mask.ether_proto);
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calc_y(tmp_y_s, rule->tuples.ether_proto,
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rule->tuples_mask.ether_proto);
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*(__le16 *)key_x = cpu_to_le16(tmp_x_s);
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*(__le16 *)key_y = cpu_to_le16(tmp_y_s);
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return true;
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case BIT(INNER_IP_TOS):
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calc_x(*key_x, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
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calc_y(*key_y, rule->tuples.ip_tos, rule->tuples_mask.ip_tos);
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return true;
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case BIT(INNER_IP_PROTO):
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calc_x(*key_x, rule->tuples.ip_proto,
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rule->tuples_mask.ip_proto);
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calc_y(*key_y, rule->tuples.ip_proto,
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rule->tuples_mask.ip_proto);
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return true;
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case BIT(INNER_SRC_IP):
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calc_x(tmp_x_l, rule->tuples.src_ip[3],
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rule->tuples_mask.src_ip[3]);
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calc_y(tmp_y_l, rule->tuples.src_ip[3],
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rule->tuples_mask.src_ip[3]);
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*(__le32 *)key_x = cpu_to_le32(tmp_x_l);
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*(__le32 *)key_y = cpu_to_le32(tmp_y_l);
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return true;
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case BIT(INNER_DST_IP):
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calc_x(tmp_x_l, rule->tuples.dst_ip[3],
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rule->tuples_mask.dst_ip[3]);
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calc_y(tmp_y_l, rule->tuples.dst_ip[3],
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rule->tuples_mask.dst_ip[3]);
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*(__le32 *)key_x = cpu_to_le32(tmp_x_l);
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*(__le32 *)key_y = cpu_to_le32(tmp_y_l);
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return true;
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case BIT(INNER_SRC_PORT):
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calc_x(tmp_x_s, rule->tuples.src_port,
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rule->tuples_mask.src_port);
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calc_y(tmp_y_s, rule->tuples.src_port,
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rule->tuples_mask.src_port);
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*(__le16 *)key_x = cpu_to_le16(tmp_x_s);
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*(__le16 *)key_y = cpu_to_le16(tmp_y_s);
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return true;
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case BIT(INNER_DST_PORT):
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calc_x(tmp_x_s, rule->tuples.dst_port,
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rule->tuples_mask.dst_port);
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calc_y(tmp_y_s, rule->tuples.dst_port,
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rule->tuples_mask.dst_port);
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*(__le16 *)key_x = cpu_to_le16(tmp_x_s);
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*(__le16 *)key_y = cpu_to_le16(tmp_y_s);
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return true;
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default:
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return false;
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}
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}
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static u32 hclge_get_port_number(enum HLCGE_PORT_TYPE port_type, u8 pf_id,
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u8 vf_id, u8 network_port_id)
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{
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u32 port_number = 0;
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if (port_type == HOST_PORT) {
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hnae3_set_field(port_number, HCLGE_PF_ID_M, HCLGE_PF_ID_S,
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pf_id);
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hnae3_set_field(port_number, HCLGE_VF_ID_M, HCLGE_VF_ID_S,
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vf_id);
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hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, HOST_PORT);
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} else {
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hnae3_set_field(port_number, HCLGE_NETWORK_PORT_ID_M,
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HCLGE_NETWORK_PORT_ID_S, network_port_id);
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hnae3_set_bit(port_number, HCLGE_PORT_TYPE_B, NETWORK_PORT);
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}
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return port_number;
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}
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static void hclge_fd_convert_meta_data(struct hclge_fd_key_cfg *key_cfg,
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__le32 *key_x, __le32 *key_y,
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struct hclge_fd_rule *rule)
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{
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u32 tuple_bit, meta_data = 0, tmp_x, tmp_y, port_number;
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u8 cur_pos = 0, tuple_size, shift_bits;
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int i;
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for (i = 0; i < MAX_META_DATA; i++) {
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tuple_size = meta_data_key_info[i].key_length;
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tuple_bit = key_cfg->meta_data_active & BIT(i);
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switch (tuple_bit) {
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case BIT(ROCE_TYPE):
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hnae3_set_bit(meta_data, cur_pos, NIC_PACKET);
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cur_pos += tuple_size;
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break;
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case BIT(DST_VPORT):
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port_number = hclge_get_port_number(HOST_PORT, 0,
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rule->vf_id, 0);
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hnae3_set_field(meta_data,
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GENMASK(cur_pos + tuple_size, cur_pos),
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cur_pos, port_number);
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cur_pos += tuple_size;
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break;
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default:
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break;
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}
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}
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calc_x(tmp_x, meta_data, 0xFFFFFFFF);
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calc_y(tmp_y, meta_data, 0xFFFFFFFF);
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shift_bits = sizeof(meta_data) * 8 - cur_pos;
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*key_x = cpu_to_le32(tmp_x << shift_bits);
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*key_y = cpu_to_le32(tmp_y << shift_bits);
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}
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/* A complete key is combined with meta data key and tuple key.
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* Meta data key is stored at the MSB region, and tuple key is stored at
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* the LSB region, unused bits will be filled 0.
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*/
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static int hclge_config_key(struct hclge_dev *hdev, u8 stage,
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struct hclge_fd_rule *rule)
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{
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struct hclge_fd_key_cfg *key_cfg = &hdev->fd_cfg.key_cfg[stage];
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u8 key_x[MAX_KEY_BYTES], key_y[MAX_KEY_BYTES];
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u8 *cur_key_x, *cur_key_y;
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int i, ret, tuple_size;
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u8 meta_data_region;
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memset(key_x, 0, sizeof(key_x));
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memset(key_y, 0, sizeof(key_y));
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cur_key_x = key_x;
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cur_key_y = key_y;
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for (i = 0 ; i < MAX_TUPLE; i++) {
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bool tuple_valid;
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u32 check_tuple;
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tuple_size = tuple_key_info[i].key_length / 8;
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check_tuple = key_cfg->tuple_active & BIT(i);
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tuple_valid = hclge_fd_convert_tuple(check_tuple, cur_key_x,
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cur_key_y, rule);
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if (tuple_valid) {
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cur_key_x += tuple_size;
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cur_key_y += tuple_size;
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}
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}
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meta_data_region = hdev->fd_cfg.max_key_length / 8 -
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MAX_META_DATA_LENGTH / 8;
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hclge_fd_convert_meta_data(key_cfg,
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(__le32 *)(key_x + meta_data_region),
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(__le32 *)(key_y + meta_data_region),
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rule);
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ret = hclge_fd_tcam_config(hdev, stage, false, rule->location, key_y,
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true);
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if (ret) {
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dev_err(&hdev->pdev->dev,
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"fd key_y config fail, loc=%d, ret=%d\n",
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rule->queue_id, ret);
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return ret;
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}
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ret = hclge_fd_tcam_config(hdev, stage, true, rule->location, key_x,
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true);
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if (ret)
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dev_err(&hdev->pdev->dev,
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"fd key_x config fail, loc=%d, ret=%d\n",
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rule->queue_id, ret);
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return ret;
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}
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static int hclge_config_action(struct hclge_dev *hdev, u8 stage,
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struct hclge_fd_rule *rule)
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{
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struct hclge_fd_ad_data ad_data;
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ad_data.ad_id = rule->location;
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if (rule->action == HCLGE_FD_ACTION_DROP_PACKET) {
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ad_data.drop_packet = true;
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ad_data.forward_to_direct_queue = false;
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ad_data.queue_id = 0;
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} else {
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ad_data.drop_packet = false;
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ad_data.forward_to_direct_queue = true;
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ad_data.queue_id = rule->queue_id;
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}
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ad_data.use_counter = false;
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ad_data.counter_id = 0;
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ad_data.use_next_stage = false;
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ad_data.next_input_key = 0;
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ad_data.write_rule_id_to_bd = true;
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ad_data.rule_id = rule->location;
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return hclge_fd_ad_config(hdev, stage, ad_data.ad_id, &ad_data);
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}
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|
||||
static void hclge_cfg_mac_mode(struct hclge_dev *hdev, bool enable)
|
||||
{
|
||||
struct hclge_desc desc;
|
||||
|
|
|
|||
|
|
@ -79,6 +79,19 @@
|
|||
#define HCLGE_VF_NUM_PER_CMD 64
|
||||
#define HCLGE_VF_NUM_PER_BYTE 8
|
||||
|
||||
enum HLCGE_PORT_TYPE {
|
||||
HOST_PORT,
|
||||
NETWORK_PORT
|
||||
};
|
||||
|
||||
#define HCLGE_PF_ID_S 0
|
||||
#define HCLGE_PF_ID_M GENMASK(2, 0)
|
||||
#define HCLGE_VF_ID_S 3
|
||||
#define HCLGE_VF_ID_M GENMASK(10, 3)
|
||||
#define HCLGE_PORT_TYPE_B 11
|
||||
#define HCLGE_NETWORK_PORT_ID_S 0
|
||||
#define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
|
||||
|
||||
/* Reset related Registers */
|
||||
#define HCLGE_MISC_RESET_STS_REG 0x20700
|
||||
#define HCLGE_MISC_VECTOR_INT_STS 0x20800
|
||||
|
|
@ -485,6 +498,11 @@ enum HCLGE_FD_PACKET_TYPE {
|
|||
ROCE_PACKET,
|
||||
};
|
||||
|
||||
enum HCLGE_FD_ACTION {
|
||||
HCLGE_FD_ACTION_ACCEPT_PACKET,
|
||||
HCLGE_FD_ACTION_DROP_PACKET,
|
||||
};
|
||||
|
||||
struct hclge_fd_key_cfg {
|
||||
u8 key_sel;
|
||||
u8 inner_sipv6_word_en;
|
||||
|
|
@ -505,6 +523,70 @@ struct hclge_fd_cfg {
|
|||
struct hclge_fd_key_cfg key_cfg[2];
|
||||
};
|
||||
|
||||
struct hclge_fd_rule_tuples {
|
||||
u8 src_mac[6];
|
||||
u8 dst_mac[6];
|
||||
u32 src_ip[4];
|
||||
u32 dst_ip[4];
|
||||
u16 src_port;
|
||||
u16 dst_port;
|
||||
u16 vlan_tag1;
|
||||
u16 ether_proto;
|
||||
u8 ip_tos;
|
||||
u8 ip_proto;
|
||||
};
|
||||
|
||||
struct hclge_fd_rule {
|
||||
struct hlist_node rule_node;
|
||||
struct hclge_fd_rule_tuples tuples;
|
||||
struct hclge_fd_rule_tuples tuples_mask;
|
||||
u32 unused_tuple;
|
||||
u32 flow_type;
|
||||
u8 action;
|
||||
u16 vf_id;
|
||||
u16 queue_id;
|
||||
u16 location;
|
||||
};
|
||||
|
||||
struct hclge_fd_ad_data {
|
||||
u16 ad_id;
|
||||
u8 drop_packet;
|
||||
u8 forward_to_direct_queue;
|
||||
u16 queue_id;
|
||||
u8 use_counter;
|
||||
u8 counter_id;
|
||||
u8 use_next_stage;
|
||||
u8 write_rule_id_to_bd;
|
||||
u8 next_input_key;
|
||||
u16 rule_id;
|
||||
};
|
||||
|
||||
/* For each bit of TCAM entry, it uses a pair of 'x' and
|
||||
* 'y' to indicate which value to match, like below:
|
||||
* ----------------------------------
|
||||
* | bit x | bit y | search value |
|
||||
* ----------------------------------
|
||||
* | 0 | 0 | always hit |
|
||||
* ----------------------------------
|
||||
* | 1 | 0 | match '0' |
|
||||
* ----------------------------------
|
||||
* | 0 | 1 | match '1' |
|
||||
* ----------------------------------
|
||||
* | 1 | 1 | invalid |
|
||||
* ----------------------------------
|
||||
* Then for input key(k) and mask(v), we can calculate the value by
|
||||
* the formulae:
|
||||
* x = (~k) & v
|
||||
* y = (k ^ ~v) & k
|
||||
*/
|
||||
#define calc_x(x, k, v) ((x) = (~(k) & (v)))
|
||||
#define calc_y(y, k, v) \
|
||||
do { \
|
||||
const typeof(k) _k_ = (k); \
|
||||
const typeof(v) _v_ = (v); \
|
||||
(y) = (_k_ ^ ~_v_) & (_k_); \
|
||||
} while (0)
|
||||
|
||||
#define HCLGE_VPORT_NUM 256
|
||||
struct hclge_dev {
|
||||
struct pci_dev *pdev;
|
||||
|
|
|
|||
Loading…
Reference in New Issue