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drm/amdgpu: split swSMU baco_reset into enter and exit 

BACO - Bus Active, Chip Off

So we can use it for power savings rather than just reset.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alex Deucher 2019-10-28 15:20:03 -04:00
parent b97e9d47e5
commit 11520f2708
9 changed files with 51 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
drivers/gpu/drm/amd/amdgpu/nv.c
View File

@ -353,7 +353,12 @@ static int nv_asic_reset(struct amdgpu_device *adev)
if (nv_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
if (!adev->in_suspend)
amdgpu_inc_vram_lost(adev);
ret = smu_baco_reset(smu);
ret = smu_baco_enter(smu);
if (ret)
return ret;
ret = smu_baco_exit(smu);
if (ret)
return ret;
} else {
if (!adev->in_suspend)
amdgpu_inc_vram_lost(adev);

10
drivers/gpu/drm/amd/amdgpu/soc15.c
View File

@ -511,9 +511,15 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
if (is_support_sw_smu(adev)) {
struct smu_context *smu = &adev->smu;
int ret;
if (smu_baco_reset(smu))
return -EIO;
ret = smu_baco_enter(smu);
if (ret)
return ret;
ret = smu_baco_exit(smu);
if (ret)
return ret;
} else {
void *pp_handle = adev->powerplay.pp_handle;
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;

20
drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
View File

@ -2456,14 +2456,28 @@ int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state)
return 0;
}
int smu_baco_reset(struct smu_context *smu)
int smu_baco_enter(struct smu_context *smu)
{
int ret = 0;
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->baco_reset)
ret = smu->ppt_funcs->baco_reset(smu);
if (smu->ppt_funcs->baco_enter)
ret = smu->ppt_funcs->baco_enter(smu);
mutex_unlock(&smu->mutex);
return ret;
}
int smu_baco_exit(struct smu_context *smu)
{
int ret = 0;
mutex_lock(&smu->mutex);
if (smu->ppt_funcs->baco_exit)
ret = smu->ppt_funcs->baco_exit(smu);
mutex_unlock(&smu->mutex);

3
drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
View File

@ -2163,7 +2163,8 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
.baco_is_support= smu_v11_0_baco_is_support,
.baco_get_state = smu_v11_0_baco_get_state,
.baco_set_state = smu_v11_0_baco_set_state,
.baco_reset = smu_v11_0_baco_reset,
.baco_enter = smu_v11_0_baco_enter,
.baco_exit = smu_v11_0_baco_exit,
.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,

6
drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h
View File

@ -546,7 +546,8 @@ struct pptable_funcs {
bool (*baco_is_support)(struct smu_context *smu);
enum smu_baco_state (*baco_get_state)(struct smu_context *smu);
int (*baco_set_state)(struct smu_context *smu, enum smu_baco_state state);
int (*baco_reset)(struct smu_context *smu);
int (*baco_enter)(struct smu_context *smu);
int (*baco_exit)(struct smu_context *smu);
int (*mode2_reset)(struct smu_context *smu);
int (*get_dpm_ultimate_freq)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t *min, uint32_t *max);
int (*set_soft_freq_limited_range)(struct smu_context *smu, enum smu_clk_type clk_type, uint32_t min, uint32_t max);
@ -628,7 +629,8 @@ bool smu_baco_is_support(struct smu_context *smu);
int smu_baco_get_state(struct smu_context *smu, enum smu_baco_state *state);
int smu_baco_reset(struct smu_context *smu);
int smu_baco_enter(struct smu_context *smu);
int smu_baco_exit(struct smu_context *smu);
int smu_mode2_reset(struct smu_context *smu);

3
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
View File

@ -248,7 +248,8 @@ enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
int smu_v11_0_baco_reset(struct smu_context *smu);
int smu_v11_0_baco_enter(struct smu_context *smu);
int smu_v11_0_baco_exit(struct smu_context *smu);
int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max);

3
drivers/gpu/drm/amd/powerplay/navi10_ppt.c
View File

@ -2109,7 +2109,8 @@ static const struct pptable_funcs navi10_ppt_funcs = {
.baco_is_support= smu_v11_0_baco_is_support,
.baco_get_state = smu_v11_0_baco_get_state,
.baco_set_state = smu_v11_0_baco_set_state,
.baco_reset = smu_v11_0_baco_reset,
.baco_enter = smu_v11_0_baco_enter,
.baco_exit = smu_v11_0_baco_exit,
.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,

9
drivers/gpu/drm/amd/powerplay/smu_v11_0.c
View File

@ -1715,7 +1715,7 @@ out:
return ret;
}
int smu_v11_0_baco_reset(struct smu_context *smu)
int smu_v11_0_baco_enter(struct smu_context *smu)
{
struct amdgpu_device *adev = smu->adev;
int ret = 0;
@ -1733,6 +1733,13 @@ int smu_v11_0_baco_reset(struct smu_context *smu)
msleep(10);
return ret;
}
int smu_v11_0_baco_exit(struct smu_context *smu)
{
int ret = 0;
ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
if (ret)
return ret;

3
drivers/gpu/drm/amd/powerplay/vega20_ppt.c
View File

@ -3257,7 +3257,8 @@ static const struct pptable_funcs vega20_ppt_funcs = {
.baco_is_support= smu_v11_0_baco_is_support,
.baco_get_state = smu_v11_0_baco_get_state,
.baco_set_state = smu_v11_0_baco_set_state,
.baco_reset = smu_v11_0_baco_reset,
.baco_enter = smu_v11_0_baco_enter,
.baco_exit = smu_v11_0_baco_exit,
.get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
.set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
.override_pcie_parameters = smu_v11_0_override_pcie_parameters,