[TG3]: Fix performance regression on 5705.
A performance regression was introduced by the following commit:
commit ee6a99b539
Author: Michael Chan <mchan@broadcom.com>
Date: Wed Jul 18 21:49:10 2007 -0700
[TG3]: Fix msi issue with kexec/kdump.
In making that change, the PCI latency timer and cache line size
registers were not restored after chip reset. On the 5705, the
latency timer gets reset to 0 during chip reset and this causes
very poor performance.
Update version to 3.84.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
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@ -64,8 +64,8 @@
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#define DRV_MODULE_NAME "tg3"
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#define DRV_MODULE_NAME "tg3"
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#define PFX DRV_MODULE_NAME ": "
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#define PFX DRV_MODULE_NAME ": "
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#define DRV_MODULE_VERSION "3.83"
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#define DRV_MODULE_VERSION "3.84"
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#define DRV_MODULE_RELDATE "October 10, 2007"
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#define DRV_MODULE_RELDATE "October 12, 2007"
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_MAC_MODE 0
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#define TG3_DEF_RX_MODE 0
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#define TG3_DEF_RX_MODE 0
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@ -5056,6 +5056,12 @@ static void tg3_restore_pci_state(struct tg3 *tp)
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pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
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pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd);
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if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
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pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
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tp->pci_cacheline_sz);
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pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
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tp->pci_lat_timer);
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}
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/* Make sure PCI-X relaxed ordering bit is clear. */
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/* Make sure PCI-X relaxed ordering bit is clear. */
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if (tp->pcix_cap) {
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if (tp->pcix_cap) {
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u16 pcix_cmd;
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u16 pcix_cmd;
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