Qualcomm Device Tree Changes for v4.10 - v2
* Add EBI2 support to MSM8660 * Add SMSC ethernet support to APQ8060 * Add support for display, pstore, iommu, and hdmi to APQ8064 * Add SDHCI node to MSM8974 Hammerhead * Add WP8548 MangOH board support (MDM9615) -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJYL+fsAAoJEFKiBbHx2RXVWcMQANE6iAFOlrwGL9RYmq35e5gi WnNxigc6pZpZWO6xz6+pVTTs6yu942T26ipKaZSVrLByDayQE6hpU4KgTPwmf25f 5sGfbFXsQEKiqzct9cFcpGTWr641gV28Uk9B6TjSlll9XkB3AWzYFB1mLqhpth/k XjiyNSkZZfPvrothgLoDg16kyUV2BthJhdbXVb+V8c3XkwDiCiPkaMb/Ee1ECgm0 8l6WHZydCXVx1QzO+1l/CJxC7BBwKL9l00gcTlbzmDS6jW8Y6GBF9rApyrmgk2GH oxnRVWtzrwFNVeYV3Gy1CVB8W1MhZQDtq0qH/cH7KbA+xpmxy3/tqZRZAdk6OV46 5YvtCIGRSnwYE/JWunedESsi9kmi6rDYPn2BwUrLULMjwzwAVX3yh4dwAHNSu9a7 nogl7qS1t+WsvEzb4rHSZTs7EDJU660TTmFXHnNDpFHNn/0xonxYWXswPxKUCLkn 2RWm6mG6+YA3KxsPqsch0sCWFNfaoZ5/HhfPnvkMI+mNtaXzjaKx6IjgkMTZV7P+ II2gBI9s40pznge0h8Aw/+lVCp1YoSYt4Z+ZhryK/BuywG5EvVVf93Sy2Z91l+Ux lmNRNoaluGiI/A5x+vdkikfqfABM96MnA8GnREOjrQGLchg42dcOB2c9zBmUWVt+ lQaL7RSqDHDFEhQ111nh =wgqF -----END PGP SIGNATURE----- Merge tag 'qcom-dts-for-4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Pull "Qualcomm Device Tree Changes for v4.10 - v2" from Andy Gross: * Add EBI2 support to MSM8660 * Add SMSC ethernet support to APQ8060 * Add support for display, pstore, iommu, and hdmi to APQ8064 * Add SDHCI node to MSM8974 Hammerhead * Add WP8548 MangOH board support (MDM9615) * tag 'qcom-dts-for-4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: add SMSC ethernet on the APQ8060 Dragonboard ARM: dts: add EBI2 to the Qualcomm MSM8660 DTSI arm: dts: qcom: apq8064-nexus7: Add pstore support to nexus7 arm: dts: qcom: apq8064-nexus7: Add DSI and panel nodes arm: dts: qcom: apq8064: Add dsi, gpu and iommu nodes arm: dts: qcom: apq8064-ifc6410: Add HDMI support arm: dts: qcom: apq8064: Add display DT nodes ARM: dts: qcom: msm8974-hammerhead: Add sdhci1 node dt-bindings: arm: Add Sierra Wireless modules bindings ARM: dts: Add WP8548 based MangOH Green board DTS ARM: dts: Add Sierra Wireless WP8548 dtsi dt-bindings: qcom: Add MDM9615 bindings ARM: dts: Add MDM9615 dtsi
This commit is contained in:
Arnd Bergmann
commit
112525b147
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@ -22,6 +22,7 @@ The 'SoC' element must be one of the following strings:
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msm8916
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msm8974
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msm8996
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mdm9615
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The 'board' element must be one of the following strings:
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@ -0,0 +1,12 @@
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Sierra Wireless Modules device tree bindings
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--------------------------------------------
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Supported Modules :
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- WP8548 : Includes MDM9615 and PM8018 in a module
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Sierra Wireless modules shall have the following properties :
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Required root node property
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- compatible: "swir,wp8548" for the WP8548 CF3 Module
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Board compatible values:
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- "swir,mangoh-green-wp8548" for the mangOH green board with the WP8548 module
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@ -633,7 +633,8 @@ dtb-$(CONFIG_ARCH_QCOM) += \
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qcom-msm8660-surf.dtb \
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qcom-msm8960-cdp.dtb \
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qcom-msm8974-lge-nexus5-hammerhead.dtb \
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qcom-msm8974-sony-xperia-honami.dtb
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qcom-msm8974-sony-xperia-honami.dtb \
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qcom-mdm9615-wp8548-mangoh-green.dtb
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dtb-$(CONFIG_ARCH_REALVIEW) += \
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arm-realview-pb1176.dtb \
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arm-realview-pb11mp.dtb \
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@ -51,6 +51,29 @@
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regulator-boot-on;
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};
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/* GPIO controlled ethernet power regulator */
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dragon_veth: xc622a331mrg {
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compatible = "regulator-fixed";
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regulator-name = "XC6222A331MR-G";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&vph>;
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gpio = <&pm8058_gpio 40 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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pinctrl-names = "default";
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pinctrl-0 = <&dragon_veth_gpios>;
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regulator-always-on;
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};
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/* VDDvario fixed regulator */
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dragon_vario: nds332p {
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compatible = "regulator-fixed";
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regulator-name = "NDS332P";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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vin-supply = <&pm8058_s3>;
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};
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/* This is a levelshifter for SDCC5 */
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dragon_vio_txb: txb0104rgyr {
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compatible = "regulator-fixed";
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@ -167,6 +190,36 @@
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bias-pull-up;
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};
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};
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dragon_ebi2_pins: ebi2 {
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/*
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* Pins used by EBI2 on the Dragonboard, actually only
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* CS2 is used by a real peripheral. CS0 is just
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* routed to a test point.
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*/
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mux0 {
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pins =
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/* "gpio39", CS1A_N this is not good to mux */
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"gpio40", /* CS2A_N */
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"gpio134"; /* CS0_N testpoint TP29 */
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function = "ebi2cs";
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};
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mux1 {
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pins =
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/* EBI2_ADDR_7 downto EBI2_ADDR_0 address bus */
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"gpio123", "gpio124", "gpio125", "gpio126",
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"gpio127", "gpio128", "gpio129", "gpio130",
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/* EBI2_DATA_15 downto EBI2_DATA_0 data bus */
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"gpio135", "gpio136", "gpio137", "gpio138",
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"gpio139", "gpio140", "gpio141", "gpio142",
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"gpio143", "gpio144", "gpio145", "gpio146",
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"gpio147", "gpio148", "gpio149", "gpio150",
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"gpio151", /* EBI2_OE_N */
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"gpio153", /* EBI2_ADV */
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"gpio157"; /* EBI2_WE_N */
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function = "ebi2";
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};
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};
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};
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qcom,ssbi@500000 {
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@ -201,6 +254,15 @@
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};
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gpio@150 {
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dragon_ethernet_gpios: ethernet-gpios {
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pinconf {
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pins = "gpio7";
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function = "normal";
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input-enable;
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bias-disable;
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power-source = <PM8058_GPIO_S3>;
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};
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};
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dragon_bmp085_gpios: bmp085-gpios {
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pinconf {
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pins = "gpio16";
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@ -238,6 +300,14 @@
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power-source = <PM8058_GPIO_S3>;
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};
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};
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dragon_veth_gpios: veth-gpios {
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pinconf {
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pins = "gpio40";
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function = "normal";
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bias-disable;
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drive-push-pull;
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};
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};
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};
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led@48 {
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@ -322,6 +392,55 @@
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};
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};
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external-bus@1a100000 {
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/* The EBI2 will instantiate first, then populate its children */
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status = "ok";
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pinctrl-names = "default";
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pinctrl-0 = <&dragon_ebi2_pins>;
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/*
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* An on-board SMSC LAN9221 chip for "debug ethernet",
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* which is actually just an ordinary ethernet on the
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* EBI2. This has a 25MHz chrystal next to it, so no
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* clocking is needed.
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*/
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ethernet-ebi2@2,0 {
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compatible = "smsc,lan9221", "smsc,lan9115";
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reg = <2 0x0 0x100>;
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/*
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* GPIO7 has interrupt 198 on the PM8058
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* The second interrupt is the PME interrupt
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* for network wakeup, connected to the TLMM.
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*/
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interrupts-extended = <&pmicintc 198 IRQ_TYPE_EDGE_FALLING>,
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<&tlmm 29 IRQ_TYPE_EDGE_RISING>;
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reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
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vdd33a-supply = <&dragon_veth>;
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vddvario-supply = <&dragon_vario>;
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pinctrl-names = "default";
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pinctrl-0 = <&dragon_ethernet_gpios>;
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phy-mode = "mii";
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reg-io-width = <2>;
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smsc,force-external-phy;
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/* IRQ on edge falling = active low */
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smsc,irq-active-low;
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smsc,irq-push-pull;
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/*
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* SLOW chipselect config
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* Delay 9 cycles (140ns@64MHz) between SMSC
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* LAN9221 Ethernet controller reads and writes
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* on CS2.
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*/
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qcom,xmem-recovery-cycles = <0>;
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qcom,xmem-write-hold-cycles = <3>;
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qcom,xmem-write-delta-cycles = <31>;
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qcom,xmem-read-delta-cycles = <28>;
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qcom,xmem-write-wait-cycles = <9>;
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qcom,xmem-read-wait-cycles = <9>;
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};
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};
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rpm@104000 {
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/*
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* Set up of the PMIC RPM regulators for this board
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@ -15,6 +15,20 @@
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stdout-path = "serial0:115200n8";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ramoops@88d00000{
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compatible = "ramoops";
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reg = <0x88d00000 0x100000>;
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record-size = <0x00020000>;
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console-size = <0x00020000>;
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ftrace-size = <0x00020000>;
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};
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};
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ext_3p3v: regulator-fixed@1 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <3300000>;
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@ -99,6 +113,7 @@
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l2 {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-always-on;
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};
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/* msm_otg-HSUSB_3p3 */
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@ -133,13 +148,14 @@
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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bias-pull-down;
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regulator-always-on;
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};
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/* pwm_power for backlight */
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l17 {
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3600000>;
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bias-pull-down;
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regulator-max-microvolt = <3000000>;
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regulator-always-on;
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};
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/* camera, qdsp6 */
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@ -184,6 +200,63 @@
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};
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};
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mdp@5100000 {
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status = "okay";
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ports {
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port@1 {
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mdp_dsi1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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};
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};
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dsi0: mdss_dsi@4700000 {
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status = "okay";
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vdda-supply = <&pm8921_l2>;/*VDD_MIPI1 to 4*/
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vdd-supply = <&pm8921_l8>;
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vddio-supply = <&pm8921_lvs7>;
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avdd-supply = <&pm8921_l11>;
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vcss-supply = <&ext_3p3v>;
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panel@0 {
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reg = <0>;
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compatible = "jdi,lt070me05000";
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vddp-supply = <&pm8921_l17>;
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iovcc-supply = <&pm8921_lvs7>;
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enable-gpios = <&pm8921_gpio 36 GPIO_ACTIVE_HIGH>;
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reset-gpios = <&tlmm_pinmux 54 GPIO_ACTIVE_LOW>;
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dcdc-en-gpios = <&pm8921_gpio 23 GPIO_ACTIVE_HIGH>;
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port {
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panel_in: endpoint {
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remote-endpoint = <&dsi0_out>;
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};
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};
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};
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ports {
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port@0 {
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dsi0_in: endpoint {
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remote-endpoint = <&mdp_dsi1_out>;
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};
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};
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port@1 {
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dsi0_out: endpoint {
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remote-endpoint = <&panel_in>;
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data-lanes = <0 1 2 3>;
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};
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};
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};
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};
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dsi-phy@4700200 {
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status = "okay";
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vddio-supply = <&pm8921_lvs7>;/*VDD_PLL2_1 to 7*/
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};
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gsbi@16200000 {
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status = "okay";
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qcom,mode = <GSBI_PROT_I2C>;
|
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|
|
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@ -43,6 +43,17 @@
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};
|
||||
};
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|
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hdmi-out {
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compatible = "hdmi-connector";
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type = "d";
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|
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port {
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hdmi_con: endpoint {
|
||||
remote-endpoint = <&hdmi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl@800000 {
|
||||
card_detect: card_detect {
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||||
|
|
@ -64,6 +75,25 @@
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|||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_pinctrl: hdmi-pinctrl {
|
||||
mux {
|
||||
pins = "gpio70", "gpio71", "gpio72";
|
||||
function = "hdmi";
|
||||
};
|
||||
|
||||
pinconf_ddc {
|
||||
pins = "gpio70", "gpio71";
|
||||
bias-pull-up;
|
||||
drive-strength = <2>;
|
||||
};
|
||||
|
||||
pinconf_hpd {
|
||||
pins = "gpio72";
|
||||
bias-pull-down;
|
||||
drive-strength = <16>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rpm@108000 {
|
||||
|
|
@ -329,5 +359,49 @@
|
|||
mmc-pwrseq = <&sdcc4_pwrseq>;
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-tx@4a00000 {
|
||||
status = "okay";
|
||||
|
||||
core-vdda-supply = <&pm8921_hdmi_switch>;
|
||||
hdmi-mux-supply = <&ext_3p3v>;
|
||||
|
||||
hpd-gpios = <&tlmm_pinmux 72 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdmi_pinctrl>;
|
||||
|
||||
ports {
|
||||
port@0 {
|
||||
endpoint {
|
||||
remote-endpoint = <&mdp_dtv_out>;
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
endpoint {
|
||||
remote-endpoint = <&hdmi_con>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi-phy@4a00400 {
|
||||
status = "okay";
|
||||
|
||||
core-vdda-supply = <&pm8921_hdmi_switch>;
|
||||
};
|
||||
|
||||
mdp@5100000 {
|
||||
status = "okay";
|
||||
|
||||
ports {
|
||||
port@3 {
|
||||
endpoint {
|
||||
remote-endpoint = <&hdmi_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1060,6 +1060,231 @@
|
|||
reg = <0x1a400000 0x100>;
|
||||
};
|
||||
|
||||
gpu: adreno-3xx@4300000 {
|
||||
compatible = "qcom,adreno-3xx";
|
||||
reg = <0x04300000 0x20000>;
|
||||
reg-names = "kgsl_3d0_reg_memory";
|
||||
interrupts = <GIC_SPI 80 0>;
|
||||
interrupt-names = "kgsl_3d0_irq";
|
||||
clock-names =
|
||||
"core_clk",
|
||||
"iface_clk",
|
||||
"mem_clk",
|
||||
"mem_iface_clk";
|
||||
clocks =
|
||||
<&mmcc GFX3D_CLK>,
|
||||
<&mmcc GFX3D_AHB_CLK>,
|
||||
<&mmcc GFX3D_AXI_CLK>,
|
||||
<&mmcc MMSS_IMEM_AHB_CLK>;
|
||||
qcom,chipid = <0x03020002>;
|
||||
|
||||
iommus = <&gfx3d 0
|
||||
&gfx3d 1
|
||||
&gfx3d 2
|
||||
&gfx3d 3
|
||||
&gfx3d 4
|
||||
&gfx3d 5
|
||||
&gfx3d 6
|
||||
&gfx3d 7
|
||||
&gfx3d 8
|
||||
&gfx3d 9
|
||||
&gfx3d 10
|
||||
&gfx3d 11
|
||||
&gfx3d 12
|
||||
&gfx3d 13
|
||||
&gfx3d 14
|
||||
&gfx3d 15
|
||||
&gfx3d 16
|
||||
&gfx3d 17
|
||||
&gfx3d 18
|
||||
&gfx3d 19
|
||||
&gfx3d 20
|
||||
&gfx3d 21
|
||||
&gfx3d 22
|
||||
&gfx3d 23
|
||||
&gfx3d 24
|
||||
&gfx3d 25
|
||||
&gfx3d 26
|
||||
&gfx3d 27
|
||||
&gfx3d 28
|
||||
&gfx3d 29
|
||||
&gfx3d 30
|
||||
&gfx3d 31
|
||||
&gfx3d1 0
|
||||
&gfx3d1 1
|
||||
&gfx3d1 2
|
||||
&gfx3d1 3
|
||||
&gfx3d1 4
|
||||
&gfx3d1 5
|
||||
&gfx3d1 6
|
||||
&gfx3d1 7
|
||||
&gfx3d1 8
|
||||
&gfx3d1 9
|
||||
&gfx3d1 10
|
||||
&gfx3d1 11
|
||||
&gfx3d1 12
|
||||
&gfx3d1 13
|
||||
&gfx3d1 14
|
||||
&gfx3d1 15
|
||||
&gfx3d1 16
|
||||
&gfx3d1 17
|
||||
&gfx3d1 18
|
||||
&gfx3d1 19
|
||||
&gfx3d1 20
|
||||
&gfx3d1 21
|
||||
&gfx3d1 22
|
||||
&gfx3d1 23
|
||||
&gfx3d1 24
|
||||
&gfx3d1 25
|
||||
&gfx3d1 26
|
||||
&gfx3d1 27
|
||||
&gfx3d1 28
|
||||
&gfx3d1 29
|
||||
&gfx3d1 30
|
||||
&gfx3d1 31>;
|
||||
|
||||
qcom,gpu-pwrlevels {
|
||||
compatible = "qcom,gpu-pwrlevels";
|
||||
qcom,gpu-pwrlevel@0 {
|
||||
qcom,gpu-freq = <450000000>;
|
||||
};
|
||||
qcom,gpu-pwrlevel@1 {
|
||||
qcom,gpu-freq = <27000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mmss_sfpb: syscon@5700000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x5700000 0x70>;
|
||||
};
|
||||
|
||||
dsi0: mdss_dsi@4700000 {
|
||||
compatible = "qcom,mdss-dsi-ctrl";
|
||||
label = "MDSS DSI CTRL->0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 82 0>;
|
||||
reg = <0x04700000 0x200>;
|
||||
reg-names = "dsi_ctrl";
|
||||
|
||||
clocks = <&mmcc DSI_M_AHB_CLK>,
|
||||
<&mmcc DSI_S_AHB_CLK>,
|
||||
<&mmcc AMP_AHB_CLK>,
|
||||
<&mmcc DSI_CLK>,
|
||||
<&mmcc DSI1_BYTE_CLK>,
|
||||
<&mmcc DSI_PIXEL_CLK>,
|
||||
<&mmcc DSI1_ESC_CLK>;
|
||||
clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
|
||||
"src_clk", "byte_clk", "pixel_clk",
|
||||
"core_clk";
|
||||
|
||||
assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
|
||||
<&mmcc DSI1_ESC_SRC>,
|
||||
<&mmcc DSI_SRC>,
|
||||
<&mmcc DSI_PIXEL_SRC>;
|
||||
assigned-clock-parents = <&dsi0_phy 0>,
|
||||
<&dsi0_phy 0>,
|
||||
<&dsi0_phy 1>,
|
||||
<&dsi0_phy 1>;
|
||||
syscon-sfpb = <&mmss_sfpb>;
|
||||
phys = <&dsi0_phy>;
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
dsi0_in: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
dsi0_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
dsi0_phy: dsi-phy@4700200 {
|
||||
compatible = "qcom,dsi-phy-28nm-8960";
|
||||
#clock-cells = <1>;
|
||||
|
||||
reg = <0x04700200 0x100>,
|
||||
<0x04700300 0x200>,
|
||||
<0x04700500 0x5c>;
|
||||
reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
|
||||
clock-names = "iface_clk";
|
||||
clocks = <&mmcc DSI_M_AHB_CLK>;
|
||||
};
|
||||
|
||||
|
||||
mdp_port0: iommu@7500000 {
|
||||
compatible = "qcom,apq8064-iommu";
|
||||
#iommu-cells = <1>;
|
||||
clock-names =
|
||||
"smmu_pclk",
|
||||
"iommu_clk";
|
||||
clocks =
|
||||
<&mmcc SMMU_AHB_CLK>,
|
||||
<&mmcc MDP_AXI_CLK>;
|
||||
reg = <0x07500000 0x100000>;
|
||||
interrupts =
|
||||
<GIC_SPI 63 0>,
|
||||
<GIC_SPI 64 0>;
|
||||
qcom,ncb = <2>;
|
||||
};
|
||||
|
||||
mdp_port1: iommu@7600000 {
|
||||
compatible = "qcom,apq8064-iommu";
|
||||
#iommu-cells = <1>;
|
||||
clock-names =
|
||||
"smmu_pclk",
|
||||
"iommu_clk";
|
||||
clocks =
|
||||
<&mmcc SMMU_AHB_CLK>,
|
||||
<&mmcc MDP_AXI_CLK>;
|
||||
reg = <0x07600000 0x100000>;
|
||||
interrupts =
|
||||
<GIC_SPI 61 0>,
|
||||
<GIC_SPI 62 0>;
|
||||
qcom,ncb = <2>;
|
||||
};
|
||||
|
||||
gfx3d: iommu@7c00000 {
|
||||
compatible = "qcom,apq8064-iommu";
|
||||
#iommu-cells = <1>;
|
||||
clock-names =
|
||||
"smmu_pclk",
|
||||
"iommu_clk";
|
||||
clocks =
|
||||
<&mmcc SMMU_AHB_CLK>,
|
||||
<&mmcc GFX3D_AXI_CLK>;
|
||||
reg = <0x07c00000 0x100000>;
|
||||
interrupts =
|
||||
<GIC_SPI 69 0>,
|
||||
<GIC_SPI 70 0>;
|
||||
qcom,ncb = <3>;
|
||||
};
|
||||
|
||||
gfx3d1: iommu@7d00000 {
|
||||
compatible = "qcom,apq8064-iommu";
|
||||
#iommu-cells = <1>;
|
||||
clock-names =
|
||||
"smmu_pclk",
|
||||
"iommu_clk";
|
||||
clocks =
|
||||
<&mmcc SMMU_AHB_CLK>,
|
||||
<&mmcc GFX3D_AXI_CLK>;
|
||||
reg = <0x07d00000 0x100000>;
|
||||
interrupts =
|
||||
<GIC_SPI 210 0>,
|
||||
<GIC_SPI 211 0>;
|
||||
qcom,ncb = <3>;
|
||||
};
|
||||
|
||||
pcie: pci@1b500000 {
|
||||
compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
|
||||
reg = <0x1b500000 0x1000
|
||||
|
|
@ -1095,6 +1320,102 @@
|
|||
reset-names = "axi", "ahb", "por", "pci", "phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdmi: hdmi-tx@4a00000 {
|
||||
compatible = "qcom,hdmi-tx-8960";
|
||||
reg = <0x04a00000 0x2f0>;
|
||||
reg-names = "core_physical";
|
||||
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mmcc HDMI_APP_CLK>,
|
||||
<&mmcc HDMI_M_AHB_CLK>,
|
||||
<&mmcc HDMI_S_AHB_CLK>;
|
||||
clock-names = "core_clk",
|
||||
"master_iface_clk",
|
||||
"slave_iface_clk";
|
||||
|
||||
phys = <&hdmi_phy>;
|
||||
phy-names = "hdmi-phy";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
hdmi_in: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
hdmi_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
hdmi_phy: hdmi-phy@4a00400 {
|
||||
compatible = "qcom,hdmi-phy-8960";
|
||||
reg = <0x4a00400 0x60>,
|
||||
<0x4a00500 0x100>;
|
||||
reg-names = "hdmi_phy",
|
||||
"hdmi_pll";
|
||||
|
||||
clocks = <&mmcc HDMI_S_AHB_CLK>;
|
||||
clock-names = "slave_iface_clk";
|
||||
};
|
||||
|
||||
mdp: mdp@5100000 {
|
||||
compatible = "qcom,mdp4";
|
||||
reg = <0x05100000 0xf0000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mmcc MDP_CLK>,
|
||||
<&mmcc MDP_AHB_CLK>,
|
||||
<&mmcc MDP_AXI_CLK>,
|
||||
<&mmcc MDP_LUT_CLK>,
|
||||
<&mmcc HDMI_TV_CLK>,
|
||||
<&mmcc MDP_TV_CLK>;
|
||||
clock-names = "core_clk",
|
||||
"iface_clk",
|
||||
"bus_clk",
|
||||
"lut_clk",
|
||||
"hdmi_clk",
|
||||
"tv_clk";
|
||||
|
||||
iommus = <&mdp_port0 0
|
||||
&mdp_port0 2
|
||||
&mdp_port1 0
|
||||
&mdp_port1 2>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
mdp_lvds_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
mdp_dsi1_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
mdp_dsi2_out: endpoint {
|
||||
};
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
mdp_dtv_out: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
#include "qcom-apq8064-pins.dtsi"
|
||||
|
|
|
|||
|
|
@ -0,0 +1,281 @@
|
|||
/*
|
||||
* Device Tree Source for mangOH Green Board with WP8548 Module
|
||||
*
|
||||
* Copyright (C) 2016 BayLibre, SAS.
|
||||
* Author : Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
#include "qcom-mdm9615-wp8548.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "MangOH Green with WP8548 Module";
|
||||
compatible = "swir,mangoh-green-wp8548", "swir,wp8548", "qcom,mdm9615";
|
||||
|
||||
aliases {
|
||||
spi0 = &gsbi3_spi;
|
||||
serial0 = &gsbi4_serial;
|
||||
serial1 = &gsbi5_serial;
|
||||
i2c0 = &gsbi5_i2c;
|
||||
mmc0 = &sdcc1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
};
|
||||
|
||||
&msmgpio {
|
||||
/* MangOH GPIO Mapping :
|
||||
* - 2 : GPIOEXP_INT2
|
||||
* - 7 : IOT1_GPIO2
|
||||
* - 8 : IOT0_GPIO4
|
||||
* - 13: IOT0_GPIO3
|
||||
* - 21: IOT1_GPIO4
|
||||
* - 22: IOT2_GPIO1
|
||||
* - 23: IOT2_GPIO2
|
||||
* - 24: IOT2_GPIO3
|
||||
* - 25: IOT1_GPIO1
|
||||
* - 32: IOT1_GPIO3
|
||||
* - 33: IOT0_GPIO2
|
||||
* - 42: IOT0_GPIO1 and SD Card Detect
|
||||
*/
|
||||
|
||||
gpioext1_pins: gpioext1_pins {
|
||||
pins {
|
||||
pins = "gpio2";
|
||||
function = "gpio";
|
||||
input-enable;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
sdc_cd_pins: sdc_cd_pins {
|
||||
pins {
|
||||
pins = "gpio42";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi3_spi {
|
||||
spi@0 {
|
||||
compatible = "swir,mangoh-iotport-spi", "spidev";
|
||||
spi-max-frequency = <24000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi5_i2c {
|
||||
mux@71 {
|
||||
compatible = "nxp,pca9548";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x71>;
|
||||
|
||||
i2c_iot0: i2c@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
i2c_iot1: i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
i2c_iot2: i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
i2c@3 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <3>;
|
||||
|
||||
usbhub: hub@8 {
|
||||
compatible = "smsc,usb3503a";
|
||||
reg = <0x8>;
|
||||
connect-gpios = <&gpioext2 1 GPIO_ACTIVE_HIGH>;
|
||||
intn-gpios = <&gpioext2 0 GPIO_ACTIVE_LOW>;
|
||||
initial-mode = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
|
||||
gpioext0: gpio@3e {
|
||||
/* GPIO Expander 0 Mapping :
|
||||
* - 0: ARDUINO_RESET_Level shift
|
||||
* - 1: BattChrgr_PG_N
|
||||
* - 2: BattGauge_GPIO
|
||||
* - 3: LED_ON (out active high)
|
||||
* - 4: ATmega_reset_GPIO
|
||||
* - 5: X
|
||||
* - 6: PCM_ANALOG_SELECT (out active high)
|
||||
* - 7: X
|
||||
* - 8: Board_rev_res1 (in)
|
||||
* - 9: Board_rev_res2 (in)
|
||||
* - 10: UART_EXP1_ENn (out active low / pull-down)
|
||||
* - 11: UART_EXP1_IN (out pull-down)
|
||||
* - 12: UART_EXP2_IN (out pull-down)
|
||||
* - 13: SDIO_SEL (out pull-down)
|
||||
* - 14: SPI_EXP1_ENn (out active low / pull-down)
|
||||
* - 15: SPI_EXP1_IN (out pull-down)
|
||||
*/
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "semtech,sx1509q";
|
||||
reg = <0x3e>;
|
||||
interrupt-parent = <&gpioext1>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
probe-reset;
|
||||
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <5>;
|
||||
|
||||
gpioext1: gpio@3f {
|
||||
/* GPIO Expander 1 Mapping :
|
||||
* - 0: GPIOEXP_INT1
|
||||
* - 1: Battery detect
|
||||
* - 2: GPIO_SCF3_RESET
|
||||
* - 3: LED_CARD_DETECT_IOT0 (in)
|
||||
* - 4: LED_CARD_DETECT_IOT1 (in)
|
||||
* - 5: LED_CARD_DETECT_IOT2 (in)
|
||||
* - 6: UIM2_PWM_SELECT
|
||||
* - 7: UIM2_M2_S_SELECT
|
||||
* - 8: TP900
|
||||
* - 9: SENSOR_INT1 (in)
|
||||
* - 10: SENSOR_INT2 (in)
|
||||
* - 11: CARD_DETECT_IOT0 (in pull-up)
|
||||
* - 12: CARD_DETECT_IOT2 (in pull-up)
|
||||
* - 13: CARD_DETECT_IOT1 (in pull-up)
|
||||
* - 14: GPIOEXP_INT3 (in active low / pull-up)
|
||||
* - 15: BattChrgr_INT_N
|
||||
*/
|
||||
pinctrl-0 = <&gpioext1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "semtech,sx1509q";
|
||||
reg = <0x3f>;
|
||||
interrupt-parent = <&msmgpio>;
|
||||
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
probe-reset;
|
||||
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@6 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <6>;
|
||||
|
||||
gpioext2: gpio@70 {
|
||||
/* GPIO Expander 2 Mapping :
|
||||
* - 0: USB_HUB_INTn
|
||||
* - 1: HUB_CONNECT
|
||||
* - 2: GPIO_IOT2_RESET (out active low / pull-up)
|
||||
* - 3: GPIO_IOT1_RESET (out active low / pull-up)
|
||||
* - 4: GPIO_IOT0_RESET (out active low / pull-up)
|
||||
* - 5: TP901
|
||||
* - 6: TP902
|
||||
* - 7: TP903
|
||||
* - 8: UART_EXP2_ENn (out active low / pull-down)
|
||||
* - 9: PCM_EXP1_ENn (out active low)
|
||||
* - 10: PCM_EXP1_SEL (out)
|
||||
* - 11: ARD_FTDI
|
||||
* - 12: TP904
|
||||
* - 13: TP905
|
||||
* - 14: TP906
|
||||
* - 15: RS232_Enable (out active high / pull-up)
|
||||
*/
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "semtech,sx1509q";
|
||||
reg = <0x70>;
|
||||
interrupt-parent = <&gpioext1>;
|
||||
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
probe-reset;
|
||||
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@7 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdcc1 {
|
||||
pinctrl-0 = <&sdc_cd_pins>;
|
||||
pinctrl-names = "default";
|
||||
disable-wp;
|
||||
cd-gpios = <&msmgpio 42 GPIO_ACTIVE_LOW>; /* Active low CD */
|
||||
};
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
/*
|
||||
* Device Tree Source for Sierra Wireless WP8548 Module
|
||||
*
|
||||
* Copyright (C) 2016 BayLibre, SAS.
|
||||
* Author : Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "qcom-mdm9615.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Sierra Wireless WP8548 Module";
|
||||
compatible = "swir,wp8548", "qcom,mdm9615";
|
||||
|
||||
memory {
|
||||
reg = <0x48000000 0x7F00000>;
|
||||
};
|
||||
};
|
||||
|
||||
&msmgpio {
|
||||
pinctrl-0 = <&reset_out_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
gsbi3_pins: gsbi3_pins {
|
||||
mux {
|
||||
pins = "gpio8", "gpio9", "gpio10", "gpio11";
|
||||
function = "gsbi3";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
gsbi4_pins: gsbi4_pins {
|
||||
mux {
|
||||
pins = "gpio12", "gpio13", "gpio14", "gpio15";
|
||||
function = "gsbi4";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
gsbi5_i2c_pins: gsbi5_i2c_pins {
|
||||
pin16 {
|
||||
pins = "gpio16";
|
||||
function = "gsbi5_i2c";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
pin17 {
|
||||
pins = "gpio17";
|
||||
function = "gsbi5_i2c";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
gsbi5_uart_pins: gsbi5_uart_pins {
|
||||
mux {
|
||||
pins = "gpio18", "gpio19";
|
||||
function = "gsbi5_uart";
|
||||
drive-strength = <8>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
reset_out_pins: reset_out_pins {
|
||||
pins {
|
||||
pins = "gpio66";
|
||||
function = "gpio";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
output-high;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pmicgpio {
|
||||
usb_vbus_5v_pins: usb_vbus_5v_pins {
|
||||
pins = "gpio4";
|
||||
function = "normal";
|
||||
output-high;
|
||||
bias-disable;
|
||||
qcom,drive-strength = <1>;
|
||||
power-source = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&gsbi3 {
|
||||
status = "ok";
|
||||
qcom,mode = <GSBI_PROT_SPI>;
|
||||
};
|
||||
|
||||
&gsbi3_spi {
|
||||
status = "ok";
|
||||
pinctrl-0 = <&gsbi3_pins>;
|
||||
pinctrl-names = "default";
|
||||
assigned-clocks = <&gcc GSBI3_QUP_CLK>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
};
|
||||
|
||||
&gsbi4 {
|
||||
status = "ok";
|
||||
qcom,mode = <GSBI_PROT_UART_W_FC>;
|
||||
};
|
||||
|
||||
&gsbi4_serial {
|
||||
status = "ok";
|
||||
pinctrl-0 = <&gsbi4_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gsbi5 {
|
||||
status = "ok";
|
||||
qcom,mode = <GSBI_PROT_I2C_UART>;
|
||||
};
|
||||
|
||||
&gsbi5_i2c {
|
||||
status = "ok";
|
||||
clock-frequency = <200000>;
|
||||
pinctrl-0 = <&gsbi5_i2c_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&gsbi5_serial {
|
||||
status = "ok";
|
||||
pinctrl-0 = <&gsbi5_uart_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
&sdcc1 {
|
||||
status = "ok";
|
||||
};
|
||||
|
|
@ -0,0 +1,557 @@
|
|||
/*
|
||||
* Device Tree Source for Qualcomm MDM9615 SoC
|
||||
*
|
||||
* Copyright (C) 2016 BayLibre, SAS.
|
||||
* Author : Neil Armstrong <narmstrong@baylibre.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/qcom,gcc-mdm9615.h>
|
||||
#include <dt-bindings/reset/qcom,gcc-mdm9615.h>
|
||||
#include <dt-bindings/mfd/qcom-rpm.h>
|
||||
#include <dt-bindings/soc/qcom,gsbi.h>
|
||||
|
||||
/ {
|
||||
model = "Qualcomm MDM9615";
|
||||
compatible = "qcom,mdm9615";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a5";
|
||||
device_type = "cpu";
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
|
||||
cpu-pmu {
|
||||
compatible = "arm,cortex-a5-pmu";
|
||||
interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
cxo_board {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
vsdcc_fixed: vsdcc-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "SDCC Power";
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <2700000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
soc: soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
compatible = "simple-bus";
|
||||
|
||||
L2: l2-cache@2040000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x02040000 0x1000>;
|
||||
arm,data-latency = <2 2 0>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@2000000 {
|
||||
compatible = "qcom,msm-qgic2";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x02000000 0x1000>,
|
||||
<0x02002000 0x1000>;
|
||||
};
|
||||
|
||||
timer@200a000 {
|
||||
compatible = "qcom,kpss-timer", "qcom,msm-timer";
|
||||
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>,
|
||||
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_EDGE_RISING)>;
|
||||
reg = <0x0200a000 0x100>;
|
||||
clock-frequency = <27000000>,
|
||||
<32768>;
|
||||
cpu-offset = <0x80000>;
|
||||
};
|
||||
|
||||
msmgpio: pinctrl@800000 {
|
||||
compatible = "qcom,mdm9615-pinctrl";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x800000 0x4000>;
|
||||
};
|
||||
|
||||
gcc: clock-controller@900000 {
|
||||
compatible = "qcom,gcc-mdm9615";
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
reg = <0x900000 0x4000>;
|
||||
};
|
||||
|
||||
lcc: clock-controller@28000000 {
|
||||
compatible = "qcom,lcc-mdm9615";
|
||||
reg = <0x28000000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
l2cc: clock-controller@2011000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x02011000 0x1000>;
|
||||
};
|
||||
|
||||
rng@1a500000 {
|
||||
compatible = "qcom,prng";
|
||||
reg = <0x1a500000 0x200>;
|
||||
clocks = <&gcc PRNG_CLK>;
|
||||
clock-names = "core";
|
||||
assigned-clocks = <&gcc PRNG_CLK>;
|
||||
assigned-clock-rates = <32000000>;
|
||||
};
|
||||
|
||||
gsbi2: gsbi@16100000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
cell-index = <2>;
|
||||
reg = <0x16100000 0x100>;
|
||||
clocks = <&gcc GSBI2_H_CLK>;
|
||||
clock-names = "iface";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gsbi2_i2c: i2c@16180000 {
|
||||
compatible = "qcom,i2c-qup-v1.1.1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x16180000 0x1000>;
|
||||
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gsbi3: gsbi@16200000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
cell-index = <3>;
|
||||
reg = <0x16200000 0x100>;
|
||||
clocks = <&gcc GSBI3_H_CLK>;
|
||||
clock-names = "iface";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gsbi3_spi: spi@16280000 {
|
||||
compatible = "qcom,spi-qup-v1.1.1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x16280000 0x1000>;
|
||||
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
|
||||
spi-max-frequency = <24000000>;
|
||||
|
||||
clocks = <&gcc GSBI3_QUP_CLK>, <&gcc GSBI3_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gsbi4: gsbi@16300000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
cell-index = <4>;
|
||||
reg = <0x16300000 0x100>;
|
||||
clocks = <&gcc GSBI4_H_CLK>;
|
||||
clock-names = "iface";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
syscon-tcsr = <&tcsr>;
|
||||
|
||||
gsbi4_serial: serial@16340000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x16340000 0x1000>,
|
||||
<0x16300000 0x1000>;
|
||||
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gsbi5: gsbi@16400000 {
|
||||
compatible = "qcom,gsbi-v1.0.0";
|
||||
cell-index = <5>;
|
||||
reg = <0x16400000 0x100>;
|
||||
clocks = <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "iface";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
syscon-tcsr = <&tcsr>;
|
||||
|
||||
gsbi5_i2c: i2c@16480000 {
|
||||
compatible = "qcom,i2c-qup-v1.1.1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x16480000 0x1000>;
|
||||
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
/* QUP clock is not initialized, set rate */
|
||||
assigned-clocks = <&gcc GSBI5_QUP_CLK>;
|
||||
assigned-clock-rates = <24000000>;
|
||||
|
||||
clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gsbi5_serial: serial@16440000 {
|
||||
compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
|
||||
reg = <0x16440000 0x1000>,
|
||||
<0x16400000 0x1000>;
|
||||
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
qcom,ssbi@500000 {
|
||||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
qcom,controller-type = "pmic-arbiter";
|
||||
|
||||
pmicintc: pmic@0 {
|
||||
compatible = "qcom,pm8018", "qcom,pm8921";
|
||||
interrupts = <GIC_PPI 226 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pwrkey@1c {
|
||||
compatible = "qcom,pm8018-pwrkey", "qcom,pm8921-pwrkey";
|
||||
reg = <0x1c>;
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <50 IRQ_TYPE_EDGE_RISING>,
|
||||
<51 IRQ_TYPE_EDGE_RISING>;
|
||||
debounce = <15625>;
|
||||
pull-up;
|
||||
};
|
||||
|
||||
pmicmpp: mpp@50 {
|
||||
compatible = "qcom,pm8018-mpp", "qcom,ssbi-mpp";
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <24 IRQ_TYPE_NONE>,
|
||||
<25 IRQ_TYPE_NONE>,
|
||||
<26 IRQ_TYPE_NONE>,
|
||||
<27 IRQ_TYPE_NONE>,
|
||||
<28 IRQ_TYPE_NONE>,
|
||||
<29 IRQ_TYPE_NONE>;
|
||||
reg = <0x50>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
rtc@11d {
|
||||
compatible = "qcom,pm8018-rtc", "qcom,pm8921-rtc";
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <39 IRQ_TYPE_EDGE_RISING>;
|
||||
reg = <0x11d>;
|
||||
allow-set-time;
|
||||
};
|
||||
|
||||
pmicgpio: gpio@150 {
|
||||
compatible = "qcom,pm8018-gpio", "qcom,ssbi-gpio";
|
||||
interrupt-parent = <&pmicintc>;
|
||||
interrupts = <24 IRQ_TYPE_NONE>,
|
||||
<25 IRQ_TYPE_NONE>,
|
||||
<26 IRQ_TYPE_NONE>,
|
||||
<27 IRQ_TYPE_NONE>,
|
||||
<28 IRQ_TYPE_NONE>,
|
||||
<29 IRQ_TYPE_NONE>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdcc1bam: dma@12182000{
|
||||
compatible = "qcom,bam-v1.3.0";
|
||||
reg = <0x12182000 0x8000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc SDC1_H_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
sdcc2bam: dma@12142000{
|
||||
compatible = "qcom,bam-v1.3.0";
|
||||
reg = <0x12142000 0x8000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gcc SDC2_H_CLK>;
|
||||
clock-names = "bam_clk";
|
||||
#dma-cells = <1>;
|
||||
qcom,ee = <0>;
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
sdcc1: sdcc@12180000 {
|
||||
status = "disabled";
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
reg = <0x12180000 0x2000>;
|
||||
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cmd_irq";
|
||||
clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
bus-width = <8>;
|
||||
max-frequency = <48000000>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
vmmc-supply = <&vsdcc_fixed>;
|
||||
dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
|
||||
dma-names = "tx", "rx";
|
||||
assigned-clocks = <&gcc SDC1_CLK>;
|
||||
assigned-clock-rates = <400000>;
|
||||
};
|
||||
|
||||
sdcc2: sdcc@12140000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
arm,primecell-periphid = <0x00051180>;
|
||||
status = "disabled";
|
||||
reg = <0x12140000 0x2000>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cmd_irq";
|
||||
clocks = <&gcc SDC2_CLK>, <&gcc SDC2_H_CLK>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
max-frequency = <48000000>;
|
||||
no-1-8-v;
|
||||
vmmc-supply = <&vsdcc_fixed>;
|
||||
dmas = <&sdcc2bam 2>, <&sdcc2bam 1>;
|
||||
dma-names = "tx", "rx";
|
||||
assigned-clocks = <&gcc SDC2_CLK>;
|
||||
assigned-clock-rates = <400000>;
|
||||
};
|
||||
};
|
||||
|
||||
tcsr: syscon@1a400000 {
|
||||
compatible = "qcom,tcsr-mdm9615", "syscon";
|
||||
reg = <0x1a400000 0x100>;
|
||||
};
|
||||
|
||||
rpm: rpm@108000 {
|
||||
compatible = "qcom,rpm-mdm9615";
|
||||
reg = <0x108000 0x1000>;
|
||||
|
||||
qcom,ipc = <&l2cc 0x8 2>;
|
||||
|
||||
interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
|
||||
<GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "ack", "err", "wakeup";
|
||||
|
||||
regulators {
|
||||
compatible = "qcom,rpm-pm8018-regulators";
|
||||
|
||||
vin_lvs1-supply = <&pm8018_s3>;
|
||||
|
||||
vdd_l7-supply = <&pm8018_s4>;
|
||||
vdd_l8-supply = <&pm8018_s3>;
|
||||
vdd_l9_l10_l11_l12-supply = <&pm8018_s5>;
|
||||
|
||||
/* Buck SMPS */
|
||||
pm8018_s1: s1 {
|
||||
regulator-min-microvolt = <500000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
qcom,switch-mode-frequency = <1600000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_s2: s2 {
|
||||
regulator-min-microvolt = <1225000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
qcom,switch-mode-frequency = <1600000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_s3: s3 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
qcom,switch-mode-frequency = <1600000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_s4: s4 {
|
||||
regulator-min-microvolt = <2100000>;
|
||||
regulator-max-microvolt = <2200000>;
|
||||
qcom,switch-mode-frequency = <1600000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_s5: s5 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
qcom,switch-mode-frequency = <1600000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
/* PMOS LDO */
|
||||
pm8018_l2: l2 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l3: l3 {
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l4: l4 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l5: l5 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l6: l6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l7: l7 {
|
||||
regulator-min-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <1900000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l8: l8 {
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l9: l9 {
|
||||
regulator-min-microvolt = <750000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l10: l10 {
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l11: l11 {
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l12: l12 {
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l13: l13 {
|
||||
regulator-min-microvolt = <1850000>;
|
||||
regulator-max-microvolt = <2950000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pm8018_l14: l14 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <2850000>;
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
/* Low Voltage Switch */
|
||||
pm8018_lvs1: lvs1 {
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -141,6 +141,23 @@
|
|||
};
|
||||
};
|
||||
|
||||
external-bus@1a100000 {
|
||||
compatible = "qcom,msm8660-ebi2";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x0 0x1a800000 0x00800000>,
|
||||
<1 0x0 0x1b000000 0x00800000>,
|
||||
<2 0x0 0x1b800000 0x00800000>,
|
||||
<3 0x0 0x1d000000 0x08000000>,
|
||||
<4 0x0 0x1c800000 0x00800000>,
|
||||
<5 0x0 0x1c000000 0x00800000>;
|
||||
reg = <0x1a100000 0x1000>, <0x1a110000 0x1000>;
|
||||
reg-names = "ebi2", "xmem";
|
||||
clocks = <&gcc EBI2_2X_CLK>, <&gcc EBI2_CLK>;
|
||||
clock-names = "ebi2x", "ebi2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qcom,ssbi@500000 {
|
||||
compatible = "qcom,ssbi";
|
||||
reg = <0x500000 0x1000>;
|
||||
|
|
|
|||
|
|
@ -224,6 +224,35 @@
|
|||
status = "ok";
|
||||
};
|
||||
|
||||
pinctrl@fd510000 {
|
||||
sdhc1_pin_a: sdhc1-pin-active {
|
||||
clk {
|
||||
pins = "sdc1_clk";
|
||||
drive-strength = <16>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
cmd-data {
|
||||
pins = "sdc1_cmd", "sdc1_data";
|
||||
drive-strength = <10>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@f9824900 {
|
||||
status = "ok";
|
||||
|
||||
vmmc-supply = <&pm8941_l20>;
|
||||
vqmmc-supply = <&pm8941_s3>;
|
||||
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhc1_pin_a>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
input-name = "gpio-keys";
|
||||
|
|
|
|||
Loading…
Reference in New Issue