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drm/msm: Convert to use resource-managed OPP API 

Use resource-managed OPP API to simplify code.

Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Link: https://lore.kernel.org/r/20210314163408.22292-12-digetx@gmail.com
Reviewed-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>
This commit is contained in:
Yangtao Li 2021-03-14 19:34:04 +03:00 committed by Rob Clark
parent 4618835230
commit 11120e9351
11 changed files with 25 additions and 68 deletions
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2
drivers/gpu/drm/msm/adreno/a5xx_gpu.c
View File

@ -1705,7 +1705,7 @@ static void check_speed_bin(struct device *dev)
nvmem_cell_put(cell);
}
dev_pm_opp_set_supported_hw(dev, &val, 1);
devm_pm_opp_set_supported_hw(dev, &val, 1);
}
struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)

2
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
View File

@ -1346,7 +1346,7 @@ static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
* The GMU handles its own frequency switching so build a list of
* available frequencies to send during initialization
*/
ret = dev_pm_opp_of_add_table(gmu->dev);
ret = devm_pm_opp_of_add_table(gmu->dev);
if (ret) {
DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
return ret;

11
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
View File

@ -1339,9 +1339,6 @@ static void a6xx_destroy(struct msm_gpu *gpu)
adreno_gpu_cleanup(adreno_gpu);
if (a6xx_gpu->opp_table)
dev_pm_opp_put_supported_hw(a6xx_gpu->opp_table);
kfree(a6xx_gpu);
}
@ -1474,7 +1471,6 @@ static u32 fuse_to_supp_hw(struct device *dev, u32 revn, u32 fuse)
static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
u32 revn)
{
struct opp_table *opp_table;
u32 supp_hw = UINT_MAX;
u16 speedbin;
int ret;
@ -1497,11 +1493,10 @@ static int a6xx_set_supported_hw(struct device *dev, struct a6xx_gpu *a6xx_gpu,
supp_hw = fuse_to_supp_hw(dev, revn, speedbin);
done:
opp_table = dev_pm_opp_set_supported_hw(dev, &supp_hw, 1);
if (IS_ERR(opp_table))
return PTR_ERR(opp_table);
ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
if (ret)
return ret;
a6xx_gpu->opp_table = opp_table;
return 0;
}

2
drivers/gpu/drm/msm/adreno/a6xx_gpu.h
View File

@ -33,8 +33,6 @@ struct a6xx_gpu {
void *llc_slice;
void *htw_llc_slice;
bool have_mmu500;
struct opp_table *opp_table;
};
#define to_a6xx_gpu(x) container_of(x, struct a6xx_gpu, base)

2
drivers/gpu/drm/msm/adreno/adreno_gpu.c
View File

@ -841,7 +841,7 @@ static void adreno_get_pwrlevels(struct device *dev,
if (!of_find_property(dev->of_node, "operating-points-v2", NULL))
ret = adreno_get_legacy_pwrlevels(dev);
else {
ret = dev_pm_opp_of_add_table(dev);
ret = devm_pm_opp_of_add_table(dev);
if (ret)
DRM_DEV_ERROR(dev, "Unable to set the OPP table\n");
}

23
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
View File

@ -1141,21 +1141,21 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
if (!dpu_kms)
return -ENOMEM;
dpu_kms->opp_table = dev_pm_opp_set_clkname(dev, "core");
if (IS_ERR(dpu_kms->opp_table))
return PTR_ERR(dpu_kms->opp_table);
ret = devm_pm_opp_set_clkname(dev, "core");
if (ret)
return ret;
/* OPP table is optional */
ret = dev_pm_opp_of_add_table(dev);
ret = devm_pm_opp_of_add_table(dev);
if (ret && ret != -ENODEV) {
dev_err(dev, "invalid OPP table in device tree\n");
goto put_clkname;
return ret;
}
mp = &dpu_kms->mp;
ret = msm_dss_parse_clock(pdev, mp);
if (ret) {
DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
goto err;
return ret;
}
platform_set_drvdata(pdev, dpu_kms);
@ -1163,7 +1163,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
if (ret) {
DPU_ERROR("failed to init kms, ret=%d\n", ret);
goto err;
return ret;
}
dpu_kms->dev = ddev;
dpu_kms->pdev = pdev;
@ -1172,11 +1172,7 @@ static int dpu_bind(struct device *dev, struct device *master, void *data)
dpu_kms->rpm_enabled = true;
priv->kms = &dpu_kms->base;
return ret;
err:
dev_pm_opp_of_remove_table(dev);
put_clkname:
dev_pm_opp_put_clkname(dpu_kms->opp_table);
return ret;
}
@ -1192,9 +1188,6 @@ static void dpu_unbind(struct device *dev, struct device *master, void *data)
if (dpu_kms->rpm_enabled)
pm_runtime_disable(&pdev->dev);
dev_pm_opp_of_remove_table(dev);
dev_pm_opp_put_clkname(dpu_kms->opp_table);
}
static const struct component_ops dpu_ops = {

2
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
View File

@ -128,8 +128,6 @@ struct dpu_kms {
struct platform_device *pdev;
bool rpm_enabled;
struct opp_table *opp_table;
struct dss_module_power mp;
/* reference count bandwidth requests, so we know when we can

30
drivers/gpu/drm/msm/dp/dp_ctrl.c
View File

@ -77,8 +77,6 @@ struct dp_ctrl_private {
struct dp_parser *parser;
struct dp_catalog *catalog;
struct opp_table *opp_table;
struct completion idle_comp;
struct completion video_comp;
};
@ -1941,20 +1939,17 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
return ERR_PTR(-ENOMEM);
}
ctrl->opp_table = dev_pm_opp_set_clkname(dev, "ctrl_link");
if (IS_ERR(ctrl->opp_table)) {
ret = devm_pm_opp_set_clkname(dev, "ctrl_link");
if (ret) {
dev_err(dev, "invalid DP OPP table in device tree\n");
/* caller do PTR_ERR(ctrl->opp_table) */
return (struct dp_ctrl *)ctrl->opp_table;
/* caller do PTR_ERR(opp_table) */
return (struct dp_ctrl *)ERR_PTR(ret);
}
/* OPP table is optional */
ret = dev_pm_opp_of_add_table(dev);
if (ret) {
ret = devm_pm_opp_of_add_table(dev);
if (ret)
dev_err(dev, "failed to add DP OPP table\n");
dev_pm_opp_put_clkname(ctrl->opp_table);
ctrl->opp_table = NULL;
}
init_completion(&ctrl->idle_comp);
init_completion(&ctrl->video_comp);
@ -1970,16 +1965,3 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
return &ctrl->dp_ctrl;
}
void dp_ctrl_put(struct dp_ctrl *dp_ctrl)
{
struct dp_ctrl_private *ctrl;
ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl);
if (ctrl->opp_table) {
dev_pm_opp_of_remove_table(ctrl->dev);
dev_pm_opp_put_clkname(ctrl->opp_table);
ctrl->opp_table = NULL;
}
}

1
drivers/gpu/drm/msm/dp/dp_ctrl.h
View File

@ -33,6 +33,5 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link,
struct dp_panel *panel, struct drm_dp_aux *aux,
struct dp_power *power, struct dp_catalog *catalog,
struct dp_parser *parser);
void dp_ctrl_put(struct dp_ctrl *dp_ctrl);
#endif /* _DP_CTRL_H_ */

5
drivers/gpu/drm/msm/dp/dp_display.c
View File

@ -747,7 +747,6 @@ static int dp_irq_hpd_handle(struct dp_display_private *dp, u32 data)
static void dp_display_deinit_sub_modules(struct dp_display_private *dp)
{
dp_debug_put(dp->debug);
dp_ctrl_put(dp->ctrl);
dp_panel_put(dp->panel);
dp_aux_put(dp->aux);
dp_audio_put(dp->audio);
@ -841,13 +840,11 @@ static int dp_init_sub_modules(struct dp_display_private *dp)
rc = PTR_ERR(dp->audio);
pr_err("failed to initialize audio, rc = %d\n", rc);
dp->audio = NULL;
goto error_audio;
goto error_ctrl;
}
return rc;
error_audio:
dp_ctrl_put(dp->ctrl);
error_ctrl:
dp_panel_put(dp->panel);
error_link:

13
drivers/gpu/drm/msm/dsi/dsi_host.c
View File

@ -114,8 +114,6 @@ struct msm_dsi_host {
struct clk *pixel_clk_src;
struct clk *byte_intf_clk;
struct opp_table *opp_table;
u32 byte_clk_rate;
u32 pixel_clk_rate;
u32 esc_clk_rate;
@ -1885,14 +1883,13 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi)
goto fail;
}
msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "byte");
if (IS_ERR(msm_host->opp_table))
return PTR_ERR(msm_host->opp_table);
ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
if (ret)
return ret;
/* OPP table is optional */
ret = dev_pm_opp_of_add_table(&pdev->dev);
ret = devm_pm_opp_of_add_table(&pdev->dev);
if (ret && ret != -ENODEV) {
dev_err(&pdev->dev, "invalid OPP table in device tree\n");
dev_pm_opp_put_clkname(msm_host->opp_table);
return ret;
}
@ -1931,8 +1928,6 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host)
mutex_destroy(&msm_host->cmd_mutex);
mutex_destroy(&msm_host->dev_mutex);
dev_pm_opp_of_remove_table(&msm_host->pdev->dev);
dev_pm_opp_put_clkname(msm_host->opp_table);
pm_runtime_disable(&msm_host->pdev->dev);
}