From 10d4e146aff9bba4e1c31c8f55eddaaa4f382643 Mon Sep 17 00:00:00 2001 From: Pankaj Bharadiya Date: Tue, 28 Jan 2020 23:45:55 +0530 Subject: [PATCH] drm/i915/display/hdmi: Make WARN* drm specific where drm_device ptr is available drm specific WARN* calls include device information in the backtrace, so we know what device the warnings originate from. Covert all the calls of WARN* with device specific drm_WARN* variants in functions where drm_device or drm_i915_private struct pointer is readily available. The conversion was done automatically with below coccinelle semantic patch. @rule1@ identifier func, T; @@ func(...) { ... struct drm_device *T = ...; <... ( -WARN( +drm_WARN(T, ...) | -WARN_ON( +drm_WARN_ON(T, ...) | -WARN_ONCE( +drm_WARN_ONCE(T, ...) | -WARN_ON_ONCE( +drm_WARN_ON_ONCE(T, ...) ) ...> } @rule2@ identifier func, T; @@ func(struct drm_device *T,...) { <... ( -WARN( +drm_WARN(T, ...) | -WARN_ON( +drm_WARN_ON(T, ...) | -WARN_ONCE( +drm_WARN_ONCE(T, ...) | -WARN_ON_ONCE( +drm_WARN_ON_ONCE(T, ...) ) ...> } @rule3@ identifier func, T; @@ func(...) { ... struct drm_i915_private *T = ...; <+... ( -WARN( +drm_WARN(&T->drm, ...) | -WARN_ON( +drm_WARN_ON(&T->drm, ...) | -WARN_ONCE( +drm_WARN_ONCE(&T->drm, ...) | -WARN_ON_ONCE( +drm_WARN_ON_ONCE(&T->drm, ...) ) ...+> } @rule4@ identifier func, T; @@ func(struct drm_i915_private *T,...) { <+... ( -WARN( +drm_WARN(&T->drm, ...) | -WARN_ON( +drm_WARN_ON(&T->drm, ...) | -WARN_ONCE( +drm_WARN_ONCE(&T->drm, ...) | -WARN_ON_ONCE( +drm_WARN_ON_ONCE(&T->drm, ...) ) ...+> } Signed-off-by: Pankaj Bharadiya Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20200128181603.27767-14-pankaj.laxminarayan.bharadiya@intel.com --- drivers/gpu/drm/i915/display/intel_hdmi.c | 52 +++++++++++++---------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index ab13cf834cc4..e68bafb76cb1 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -72,17 +72,19 @@ assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi) enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE; - WARN(intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, - "HDMI port enabled, expecting disabled\n"); + drm_WARN(dev, + intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, + "HDMI port enabled, expecting disabled\n"); } static void assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { - WARN(intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & - TRANS_DDI_FUNC_ENABLE, - "HDMI transcoder function enabled, expecting disabled\n"); + drm_WARN(&dev_priv->drm, + intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & + TRANS_DDI_FUNC_ENABLE, + "HDMI transcoder function enabled, expecting disabled\n"); } struct intel_hdmi *enc_to_intel_hdmi(struct intel_encoder *encoder) @@ -218,7 +220,8 @@ static void g4x_write_infoframe(struct intel_encoder *encoder, u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); int i; - WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); + drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), + "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); @@ -291,7 +294,8 @@ static void ibx_write_infoframe(struct intel_encoder *encoder, u32 val = intel_de_read(dev_priv, reg); int i; - WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); + drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), + "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); @@ -369,7 +373,8 @@ static void cpt_write_infoframe(struct intel_encoder *encoder, u32 val = intel_de_read(dev_priv, reg); int i; - WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); + drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), + "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); @@ -446,7 +451,8 @@ static void vlv_write_infoframe(struct intel_encoder *encoder, u32 val = intel_de_read(dev_priv, reg); int i; - WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n"); + drm_WARN(&dev_priv->drm, !(val & VIDEO_DIP_ENABLE), + "Writing DIP with CTL reg disabled\n"); val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */ val |= g4x_infoframe_index(type); @@ -528,7 +534,7 @@ static void hsw_write_infoframe(struct intel_encoder *encoder, data_size = hsw_dip_data_size(dev_priv, type); - WARN_ON(len > data_size); + drm_WARN_ON(&dev_priv->drm, len > data_size); val &= ~hsw_infoframe_enable(type); intel_de_write(dev_priv, ctl_reg, val); @@ -852,7 +858,7 @@ intel_hdmi_compute_drm_infoframe(struct intel_encoder *encoder, } ret = hdmi_drm_infoframe_check(frame); - if (WARN_ON(ret)) + if (drm_WARN_ON(&dev_priv->drm, ret)) return false; return true; @@ -1070,9 +1076,9 @@ static void ibx_set_infoframes(struct intel_encoder *encoder, } if (port != (val & VIDEO_DIP_PORT_MASK)) { - WARN(val & VIDEO_DIP_ENABLE, - "DIP already enabled on port %c\n", - (val & VIDEO_DIP_PORT_MASK) >> 29); + drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, + "DIP already enabled on port %c\n", + (val & VIDEO_DIP_PORT_MASK) >> 29); val &= ~VIDEO_DIP_PORT_MASK; val |= port; } @@ -1177,9 +1183,9 @@ static void vlv_set_infoframes(struct intel_encoder *encoder, } if (port != (val & VIDEO_DIP_PORT_MASK)) { - WARN(val & VIDEO_DIP_ENABLE, - "DIP already enabled on port %c\n", - (val & VIDEO_DIP_PORT_MASK) >> 29); + drm_WARN(&dev_priv->drm, val & VIDEO_DIP_ENABLE, + "DIP already enabled on port %c\n", + (val & VIDEO_DIP_PORT_MASK) >> 29); val &= ~VIDEO_DIP_PORT_MASK; val |= port; } @@ -3011,7 +3017,7 @@ static u8 icl_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port) else if (intel_phy_is_tc(dev_priv, phy)) return GMBUS_PIN_9_TC1_ICP + intel_port_to_tc(dev_priv, port); - WARN(1, "Unknown port:%c\n", port_name(port)); + drm_WARN(&dev_priv->drm, 1, "Unknown port:%c\n", port_name(port)); return GMBUS_PIN_2_BXT; } @@ -3148,13 +3154,13 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, DRM_DEBUG_KMS("Adding HDMI connector on [ENCODER:%d:%s]\n", intel_encoder->base.base.id, intel_encoder->base.name); - if (INTEL_GEN(dev_priv) < 12 && WARN_ON(port == PORT_A)) + if (INTEL_GEN(dev_priv) < 12 && drm_WARN_ON(dev, port == PORT_A)) return; - if (WARN(intel_dig_port->max_lanes < 4, - "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", - intel_dig_port->max_lanes, intel_encoder->base.base.id, - intel_encoder->base.name)) + if (drm_WARN(dev, intel_dig_port->max_lanes < 4, + "Not enough lanes (%d) for HDMI on [ENCODER:%d:%s]\n", + intel_dig_port->max_lanes, intel_encoder->base.base.id, + intel_encoder->base.name)) return; intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(intel_encoder);