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Qualcomm ARM64 updates for v6.4 

PCI I/O and MEM ranges are corrected across all targets with PCIe
 enabled. Likewise is CPU clocks defined to be provided from CPUfreq for
 a wide range of platforms, to satisfy the OPP definitions, and LLCC bank
 information is corrected for all relevant platforms.
 
 IPQ5332 gains SMEM, CPUfreq and support for triggering download mode.
 The MI01.2 board is introduced.
 
 On MSM8916 WCN compatibles are moved to be defined per board, to avoid
 issues when boards rely on the incorrect defaults. Support for Yiming
 UZ801 4G modem stick is introduced.
 
 XO clock is defined and fed to RPMCC on MSM8953 and MSM8976, to ensure
 clock trees are properly rooted. DSI clocks feeding into gcc are
 described on MSM8953.
 
 On MSM8996 the external audio components are moved from the SoC dtsi. A
 few DWC3 quirks are added.
 
 On MSM8998 GPIO names are introduced for Sony Xperia XZ Premium, XZ1 and
 XZ1 Compact. A numbe of boards have GPIO keys properly marked as
 wakeup-source.
 
 The SA8775P platform is extended with CPUfreq, UARTs, I2C controllers,
 SPI controllers, SPMI and PMICs, PDC support. The associated PMICs gains
 reset and power key support, as well as thermal zones defined. Nodes are
 sorted. On top of this the SA8775P Ride board/platform is introduced.
 
 On SC7180 and SC7280 a range of fixes coming from DeviceTree validation are
 introduced, some clearing up unused properties, others correcting
 errors. A number of Google rev0 boards on SC7180 are dropped, as these
 are not considered to be in use by anyone anymore.
 
 On SC8280XP RTC support is introduced and enabled for the CRD and Lenovo
 Thinkpad X13s. It gains another UART, upon which Bluetooth is enabled on
 the Lenovo ThinkPad X13s. The touchpad definition is altered to attempt
 to probe both devices seen in the wild. A number of bug fixes are also
 introduced, and the regulator definitions on X13s are corrected.
 
 On SDM845 dynamic power coefficients are improved. BWMON compatible is
 corrected. Xiaomi Pocophone F1 gains notification LED. Sony Xperia XZ2,
 XZ2 Compact and XZ3 gains display, touchscreen, gpu and remoteproc
 support. OnePlus 6 and 6T gains hall sensor.
 
 GPU clock controller and remoteproc nodes are added for SM6115. CPU
 clock are defined to come from CPUfreq. Board-specific USB-properties
 are moved out of the SoC dtsi.
 
 On SM6375 L3 scaling, IMEM, RMTFS, RPM sleep stats, Tsens, modem
 remoteproc and WiFi nodes are added. Tsens thermal zones are defined and additional low power states
 are defined. Sony Xperia 10 IV gains volume down key support.
 
 On SM8150 another UART is introduced, to be used by GNSS on the SA8155
 ADP. Support for the Flash LED block in PM8150L is added.
 
 On SM8250 TPDM MM and PRNG is defined, MHI region is added to PCIe node.
 A few bug fixes are introduced after Devicetree validation.
 
 The DisplayPort controller on both SM8350 and SM8450 is defined and the
 related QMP instance is transitioned to the USB3/DP combo variant. IMEM
 and PIL info is introduced, for post mortem debugging of remoteprocs. On
 the HDK PMIC GLINK is enabled and role switch is enabled. Some audio
 resources are corrected.
 
 A typo in the USB role property of the Microsoft Surface is corrected,
 thanks to DeviceTree validation.
 
 PCIe controllers and PHYs descriptions are corrected, and pinctrl state
 definitions are moved from the soc to the board definition. BWMON
 compatibles are corrected. PM8550B gains the definition of the eUSB2
 repeater and this is enabled on the MTP. PMIC GLINK is also defined for
 the MTP and connected to DWC3, for role switching support.
 
 In addition to this, a range of cleanups based on Devicetree validation
 is introduced.
 
 A few clock bindings are introduced, from topic-branches shared with the
 clock tree, to aid introduction of references to these.
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Merge tag 'qcom-arm64-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Qualcomm ARM64 updates for v6.4

PCI I/O and MEM ranges are corrected across all targets with PCIe
enabled. Likewise is CPU clocks defined to be provided from CPUfreq for
a wide range of platforms, to satisfy the OPP definitions, and LLCC bank
information is corrected for all relevant platforms.

IPQ5332 gains SMEM, CPUfreq and support for triggering download mode.
The MI01.2 board is introduced.

On MSM8916 WCN compatibles are moved to be defined per board, to avoid
issues when boards rely on the incorrect defaults. Support for Yiming
UZ801 4G modem stick is introduced.

XO clock is defined and fed to RPMCC on MSM8953 and MSM8976, to ensure
clock trees are properly rooted. DSI clocks feeding into gcc are
described on MSM8953.

On MSM8996 the external audio components are moved from the SoC dtsi. A
few DWC3 quirks are added.

On MSM8998 GPIO names are introduced for Sony Xperia XZ Premium, XZ1 and
XZ1 Compact. A numbe of boards have GPIO keys properly marked as
wakeup-source.

The SA8775P platform is extended with CPUfreq, UARTs, I2C controllers,
SPI controllers, SPMI and PMICs, PDC support. The associated PMICs gains
reset and power key support, as well as thermal zones defined. Nodes are
sorted. On top of this the SA8775P Ride board/platform is introduced.

On SC7180 and SC7280 a range of fixes coming from DeviceTree validation are
introduced, some clearing up unused properties, others correcting
errors. A number of Google rev0 boards on SC7180 are dropped, as these
are not considered to be in use by anyone anymore.

On SC8280XP RTC support is introduced and enabled for the CRD and Lenovo
Thinkpad X13s. It gains another UART, upon which Bluetooth is enabled on
the Lenovo ThinkPad X13s. The touchpad definition is altered to attempt
to probe both devices seen in the wild. A number of bug fixes are also
introduced, and the regulator definitions on X13s are corrected.

On SDM845 dynamic power coefficients are improved. BWMON compatible is
corrected. Xiaomi Pocophone F1 gains notification LED. Sony Xperia XZ2,
XZ2 Compact and XZ3 gains display, touchscreen, gpu and remoteproc
support. OnePlus 6 and 6T gains hall sensor.

GPU clock controller and remoteproc nodes are added for SM6115. CPU
clock are defined to come from CPUfreq. Board-specific USB-properties
are moved out of the SoC dtsi.

On SM6375 L3 scaling, IMEM, RMTFS, RPM sleep stats, Tsens, modem
remoteproc and WiFi nodes are added. Tsens thermal zones are defined and additional low power states
are defined. Sony Xperia 10 IV gains volume down key support.

On SM8150 another UART is introduced, to be used by GNSS on the SA8155
ADP. Support for the Flash LED block in PM8150L is added.

On SM8250 TPDM MM and PRNG is defined, MHI region is added to PCIe node.
A few bug fixes are introduced after Devicetree validation.

The DisplayPort controller on both SM8350 and SM8450 is defined and the
related QMP instance is transitioned to the USB3/DP combo variant. IMEM
and PIL info is introduced, for post mortem debugging of remoteprocs. On
the HDK PMIC GLINK is enabled and role switch is enabled. Some audio
resources are corrected.

A typo in the USB role property of the Microsoft Surface is corrected,
thanks to DeviceTree validation.

PCIe controllers and PHYs descriptions are corrected, and pinctrl state
definitions are moved from the soc to the board definition. BWMON
compatibles are corrected. PM8550B gains the definition of the eUSB2
repeater and this is enabled on the MTP. PMIC GLINK is also defined for
the MTP and connected to DWC3, for role switching support.

In addition to this, a range of cleanups based on Devicetree validation
is introduced.

A few clock bindings are introduced, from topic-branches shared with the
clock tree, to aid introduction of references to these.

* tag 'qcom-arm64-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (256 commits)
  arm64: dts: qcom: sc8280xp-x13s: Add bluetooth
  arm64: dts: qcom: sc8280xp: Define uart2
  arm64: dts: qcom: sc8280xp: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sm8250: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sdm845: Add "mhi" region to the PCIe nodes
  arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
  arm64: dts: qcom: sa8775p: add PMIC GPIO controller nodes
  arm64: dts: qcom: sa8775p: pmic: add thermal zones
  arm64: dts: qcom: sa8775p: pmic: add support for the pmm8654 RESIN input
  arm64: dts: qcom: sa8775p: pmic: add the power key
  arm64: dts: qcom: sa8775p: add the Power On device node
  arm64: dts: qcom: sa8775p: add support for the on-board PMICs
  arm64: dts: qcom: sa8775p: add the spmi node
  arm64: dts: qcom: sa8775p: add the pdc node
  arm64: dts: qcom: sa8775p: sort soc nodes by reg property
  arm64: dts: qcom: sa8775p: pad reg properties to 8 digits
  arm64: dts: qcom: sc8280xp: correct Soundwire wakeup interrupt name
  arm64: dts: qcom: sdm845-tama: Enable GPI_DMA0/1
  arm64: dts: qcom: sdm845-tama: Enable GPU
  arm64: dts: qcom: sdm845-tama: Enable remoteprocs
  ...

Link: https://lore.kernel.org/r/20230410170233.5931-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2023-04-14 17:54:35 +02:00
parent a8127d2aae 105560b4fc
commit 10678a0751
145 changed files with 6598 additions and 1432 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53
Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml Normal file
View File

@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ5332
maintainers:
- Bjorn Andersson <andersson@kernel.org>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ5332.
See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
allOf:
- $ref: qcom,gcc.yaml#
properties:
compatible:
const: qcom,ipq5332-gcc
clocks:
items:
- description: Board XO clock source
- description: Sleep clock source
- description: PCIE 2lane PHY pipe clock source
- description: PCIE 2lane x1 PHY pipe clock source (For second lane)
- description: USB PCIE wrapper pipe clock source
required:
- compatible
- clocks
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,ipq5332-gcc";
reg = <0x01800000 0x80000>;
clocks = <&xo_board>,
<&sleep_clk>,
<&pcie_2lane_phy_pipe_clk>,
<&pcie_2lane_phy_pipe_clk_x1>,
<&usb_pcie_wrapper_pipe_clk>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
};
...

58
Documentation/devicetree/bindings/clock/qcom,sm6115-gpucc.yaml Normal file
View File

@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6115
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm graphics clock control module provides clocks, resets and power
domains on Qualcomm SoCs.
See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h
properties:
compatible:
enum:
- qcom,sm6115-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 main div source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm6115.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
clock-controller@5990000 {
compatible = "qcom,sm6115-gpucc";
reg = <0x05990000 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...

64
Documentation/devicetree/bindings/clock/qcom,sm6125-gpucc.yaml Normal file
View File

@ -0,0 +1,64 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6125
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm graphics clock control module provides clocks and power domains on
Qualcomm SoCs.
See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
properties:
compatible:
enum:
- qcom,sm6125-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
'#clock-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sm6125.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
soc {
#address-cells = <1>;
#size-cells = <1>;
clock-controller@5990000 {
compatible = "qcom,sm6125-gpucc";
reg = <0x05990000 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>;
#clock-cells = <1>;
#power-domain-cells = <1>;
};
};
...

60
Documentation/devicetree/bindings/clock/qcom,sm6375-gpucc.yaml Normal file
View File

@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Graphics Clock & Reset Controller on SM6375
maintainers:
- Konrad Dybcio <konrad.dybcio@linaro.org>
description: |
Qualcomm graphics clock control module provides clocks, resets and power
domains on Qualcomm SoCs.
See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
properties:
compatible:
enum:
- qcom,sm6375-gpucc
clocks:
items:
- description: Board XO source
- description: GPLL0 main branch source
- description: GPLL0 div branch source
- description: SNoC DVM GFX source
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm6375-gcc.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clock-controller@5990000 {
compatible = "qcom,sm6375-gpucc";
reg = <0 0x05990000 0 0x9000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>,
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
};
...

14
arch/arm64/boot/dts/qcom/Makefile
View File

@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8094-sony-xperia-kitakami-karin_windy.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
dtb-$(CONFIG_ARCH_QCOM) += apq8096-ifc6640.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq5332-mi01.2.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq6018-cp01-c1.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk01.dtb
dtb-$(CONFIG_ARCH_QCOM) += ipq8074-hk10-c1.dtb
@ -28,6 +29,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-uf896.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-thwc-ufi001c.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-yiming-uz801v3.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-motorola-potter.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-daisy.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8953-xiaomi-mido.dtb
@ -75,6 +77,7 @@ dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb
@ -83,9 +86,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-kingoftown.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-lte.dtb
@ -100,10 +101,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-r9.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r4.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r5.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-limozeen-nots-r9.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-auo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev0-boe.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-auo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-mrbland-rev1-boe.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-parade.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-lte-ti.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pazquel-parade.dtb
@ -118,8 +115,6 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-quackingstick-r0-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-boe.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev0-inx.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-boe.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-wormdingler-rev1-inx-rt5682s.dtb
@ -200,3 +195,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb

15
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
View File

@ -325,12 +325,6 @@
linux,code = <KEY_VOLUMEDOWN>;
};
&pronto {
status = "okay";
firmware-name = "qcom/apq8016/wcnss.mbn";
};
&sdhc_1 {
status = "okay";
@ -411,10 +405,19 @@
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
};
&wcnss {
status = "okay";
firmware-name = "qcom/apq8016/wcnss.mbn";
};
&wcnss_ctrl {
firmware-name = "qcom/apq8016/WCNSS_qcom_wlan_nv_sbc.bin";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
/* Enable CoreSight */
&cti0 { status = "okay"; };
&cti1 { status = "okay"; };

65
arch/arm64/boot/dts/qcom/apq8096-db820c.dts
View File

@ -63,7 +63,6 @@
};
clocks {
compatible = "simple-bus";
divclk4: divclk4 {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -146,7 +145,6 @@
&blsp1_spi1 {
/* On Low speed expansion */
label = "LS-SPI0";
status = "okay";
};
@ -183,7 +181,6 @@
&blsp2_spi6 {
/* On High speed expansion */
label = "HS-SPI1";
status = "okay";
};
@ -706,8 +703,7 @@
&pmi8994_spmi_regulators {
vdd_s2-supply = <&vph_pwr>;
vdd_gfx: s2@1700 {
reg = <0x1700 0x100>;
vdd_gfx: s2 {
regulator-name = "VDD_GFX";
regulator-min-microvolt = <980000>;
regulator-max-microvolt = <980000>;
@ -974,6 +970,50 @@
};
};
&slim_msm {
status = "okay";
slim@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
tasha_ifd: tas-ifd@0,0 {
compatible = "slim217,1a0";
reg = <0 0>;
};
wcd9335: codec@1,0 {
compatible = "slim217,1a0";
reg = <1 0>;
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
<&rpmcc RPM_SMD_BB_CLK1>;
interrupt-parent = <&tlmm>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
pinctrl-names = "default";
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
slim-ifc-dev = <&tasha_ifd>;
#sound-dai-cells = <1>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
};
};
};
&sound {
compatible = "qcom,apq8096-sndcard";
model = "DB820c";
@ -1026,7 +1066,7 @@
platform {
sound-dai = <&q6routing>;
};
};
codec {
sound-dai = <&wcd9335 AIF4_PB>;
@ -1095,21 +1135,8 @@
vdda-phy-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
};
&venus {
status = "okay";
};
&wcd9335 {
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
<&rpmcc RPM_SMD_BB_CLK1>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
};

75
arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts Normal file
View File

@ -0,0 +1,75 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* IPQ5332 AP-MI01.2 board device tree source
*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
/dts-v1/;
#include "ipq5332.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ5332 MI01.2";
compatible = "qcom,ipq5332-ap-mi01.2", "qcom,ipq5332";
aliases {
serial0 = &blsp1_uart0;
};
chosen {
stdout-path = "serial0";
};
};
&blsp1_uart0 {
pinctrl-0 = <&serial_0_pins>;
pinctrl-names = "default";
status = "okay";
};
&sdhc {
bus-width = <4>;
max-frequency = <192000000>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
pinctrl-0 = <&sdc_default_state>;
pinctrl-names = "default";
status = "okay";
};
&sleep_clk {
clock-frequency = <32000>;
};
&xo_board {
clock-frequency = <24000000>;
};
/* PINCTRL */
&tlmm {
sdc_default_state: sdc-default-state {
clk-pins {
pins = "gpio13";
function = "sdc_clk";
drive-strength = <8>;
bias-disable;
};
cmd-pins {
pins = "gpio12";
function = "sdc_cmd";
drive-strength = <8>;
bias-pull-up;
};
data-pins {
pins = "gpio8", "gpio9", "gpio10", "gpio11";
function = "sdc_data";
drive-strength = <8>;
bias-pull-up;
};
};
};

320
arch/arm64/boot/dts/qcom/ipq5332.dtsi Normal file
View File

@ -0,0 +1,320 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* IPQ5332 device tree source
*
* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#include <dt-bindings/clock/qcom,apss-ipq.h>
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
clocks {
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
xo_board: xo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
operating-points-v2 = <&cpu_opp_table>;
};
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
};
};
firmware {
scm {
compatible = "qcom,scm-ipq5332", "qcom,scm";
qcom,dload-mode = <&tcsr 0x6100>;
};
};
memory@40000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
reg = <0x0 0x40000000 0x0 0x0>;
};
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2";
opp-shared;
opp-1488000000 {
opp-hz = /bits/ 64 <1488000000>;
clock-latency-ns = <200000>;
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
tz_mem: tz@4a600000 {
reg = <0x0 0x4a600000 0x0 0x200000>;
no-map;
};
smem@4a800000 {
compatible = "qcom,smem";
reg = <0x0 0x4a800000 0x0 0x00100000>;
no-map;
hwlocks = <&tcsr_mutex 0>;
};
};
soc@0 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5332-tlmm";
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 53>;
interrupt-controller;
#interrupt-cells = <2>;
serial_0_pins: serial0-state {
pins = "gpio18", "gpio19";
function = "blsp0_uart0";
drive-strength = <8>;
bias-pull-up;
};
};
gcc: clock-controller@1800000 {
compatible = "qcom,ipq5332-gcc";
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&xo_board>,
<&sleep_clk>,
<0>,
<0>,
<0>;
};
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01905000 0x20000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1937000 {
compatible = "qcom,tcsr-ipq5332", "syscon";
reg = <0x01937000 0x21000>;
};
sdhc: mmc@7804000 {
compatible = "qcom,ipq5332-sdhci", "qcom,sdhci-msm-v5";
reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq", "pwr_irq";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
clock-names = "iface", "core", "xo";
status = "disabled";
};
blsp1_uart0: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x078af000 0x200>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
status = "disabled";
};
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
reg = <0x0b000000 0x1000>, /* GICD */
<0x0b002000 0x1000>, /* GICC */
<0x0b001000 0x1000>, /* GICH */
<0x0b004000 0x1000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x0b00c000 0x3000>;
v2m0: v2m@0 {
compatible = "arm,gic-v2m-frame";
reg = <0x00000000 0xffd>;
msi-controller;
};
v2m1: v2m@1000 {
compatible = "arm,gic-v2m-frame";
reg = <0x00001000 0xffd>;
msi-controller;
};
v2m2: v2m@2000 {
compatible = "arm,gic-v2m-frame";
reg = <0x00002000 0xffd>;
msi-controller;
};
};
apcs_glb: mailbox@b111000 {
compatible = "qcom,ipq5332-apcs-apps-global",
"qcom,ipq6018-apcs-apps-global";
reg = <0x0b111000 0x1000>;
#clock-cells = <1>;
clocks = <&a53pll>, <&xo_board>;
clock-names = "pll", "xo";
#mbox-cells = <1>;
};
a53pll: clock@b116000 {
compatible = "qcom,ipq5332-a53pll";
reg = <0x0b116000 0x40>;
#clock-cells = <0>;
clocks = <&xo_board>;
clock-names = "xo";
};
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
frame@b120000 {
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <0>;
};
frame@b123000 {
reg = <0x0b123000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <1>;
status = "disabled";
};
frame@b124000 {
reg = <0x0b124000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <2>;
status = "disabled";
};
frame@b125000 {
reg = <0x0b125000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <3>;
status = "disabled";
};
frame@b126000 {
reg = <0x0b126000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <4>;
status = "disabled";
};
frame@b127000 {
reg = <0x0b127000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <5>;
status = "disabled";
};
frame@b128000 {
reg = <0x0b128000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <6>;
status = "disabled";
};
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
};

1
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
View File

@ -35,7 +35,6 @@
};
&blsp1_spi1 {
cs-select = <0>;
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "okay";

4
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@ -738,8 +738,8 @@
phys = <&pcie_phy0>;
phy-names = "pciephy";
ranges = <0x81000000 0 0x20200000 0 0x20200000 0 0x10000>,
<0x82000000 0 0x20220000 0 0x20220000 0 0xfde0000>;
ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>,
<0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";

4
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
View File

@ -62,11 +62,11 @@
perst-gpios = <&tlmm 58 GPIO_ACTIVE_LOW>;
};
&pcie_phy0 {
&pcie_qmp0 {
status = "okay";
};
&pcie_phy1 {
&pcie_qmp1 {
status = "okay";
};

4
arch/arm64/boot/dts/qcom/ipq8074-hk10.dtsi
View File

@ -48,11 +48,11 @@
perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
};
&pcie_phy0 {
&pcie_qmp0 {
status = "okay";
};
&pcie_phy1 {
&pcie_qmp1 {
status = "okay";
};

13
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@ -397,7 +397,6 @@
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
sdhc_1: mmc@7824900 {
@ -780,10 +779,8 @@
phys = <&pcie_phy1>;
phy-names = "pciephy";
ranges = <0x81000000 0 0x10200000 0x10200000
0 0x10000>, /* downstream I/O */
<0x82000000 0 0x10220000 0x10220000
0 0xfde0000>; /* non-prefetchable memory */
ranges = <0x81000000 0x0 0x00000000 0x10200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x10220000 0x10220000 0x0 0xfde0000>; /* MEM */
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
@ -844,10 +841,8 @@
phys = <&pcie_phy0>;
phy-names = "pciephy";
ranges = <0x81000000 0 0x20200000 0x20200000
0 0x10000>, /* downstream I/O */
<0x82000000 0 0x20220000 0x20220000
0 0xfde0000>; /* non-prefetchable memory */
ranges = <0x81000000 0x0 0x00000000 0x20200000 0x0 0x10000>, /* I/O */
<0x82000000 0x0 0x20220000 0x20220000 0x0 0xfde0000>; /* MEM */
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";

12
arch/arm64/boot/dts/qcom/msm8916-acer-a1-724.dts
View File

@ -118,10 +118,6 @@
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
@ -149,6 +145,14 @@
extcon = <&usb_id>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

12
arch/arm64/boot/dts/qcom/msm8916-alcatel-idol347.dts
View File

@ -160,10 +160,6 @@
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
@ -191,6 +187,14 @@
extcon = <&usb_id>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

12
arch/arm64/boot/dts/qcom/msm8916-asus-z00l.dts
View File

@ -128,10 +128,6 @@
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
@ -159,6 +155,14 @@
extcon = <&usb_id>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

12
arch/arm64/boot/dts/qcom/msm8916-gplus-fl8005a.dts
View File

@ -118,10 +118,6 @@
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
@ -149,6 +145,14 @@
extcon = <&usb_id>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

12
arch/arm64/boot/dts/qcom/msm8916-huawei-g7.dts
View File

@ -227,10 +227,6 @@
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
@ -312,6 +308,14 @@
qcom,hphl-jack-type-normally-open;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

12
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
View File

@ -231,10 +231,6 @@
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
@ -263,6 +259,14 @@
extcon = <&pm8916_usbin>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

12
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8910.dts
View File

@ -99,10 +99,6 @@
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
@ -130,6 +126,14 @@
extcon = <&usb_id>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

22
arch/arm64/boot/dts/qcom/msm8916-pm8916.dtsi
View File

@ -20,17 +20,6 @@
pll-supply = <&pm8916_l7>;
};
&pronto {
vddpx-supply = <&pm8916_l7>;
iris {
vddxo-supply = <&pm8916_l7>;
vddrfa-supply = <&pm8916_s3>;
vddpa-supply = <&pm8916_l9>;
vdddig-supply = <&pm8916_l5>;
};
};
&sdhc_1 {
vmmc-supply = <&pm8916_l8>;
vqmmc-supply = <&pm8916_l5>;
@ -46,6 +35,17 @@
v3p3-supply = <&pm8916_l13>;
};
&wcnss {
vddpx-supply = <&pm8916_l7>;
};
&wcnss_iris {
vddxo-supply = <&pm8916_l7>;
vddrfa-supply = <&pm8916_s3>;
vddpa-supply = <&pm8916_l9>;
vdddig-supply = <&pm8916_l5>;
};
&rpm_requests {
smd_rpm_regulators: regulators {
compatible = "qcom,rpm-pm8916-regulators";

4
arch/arm64/boot/dts/qcom/msm8916-samsung-a2015-common.dtsi
View File

@ -252,10 +252,6 @@
linux,code = <KEY_VOLUMEDOWN>;
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";

8
arch/arm64/boot/dts/qcom/msm8916-samsung-a3u-eur.dts
View File

@ -112,6 +112,14 @@
status = "okay";
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&msmgpio {
panel_vdd3_default: panel-vdd3-default-state {
pins = "gpio9";

14
arch/arm64/boot/dts/qcom/msm8916-samsung-a5u-eur.dts
View File

@ -54,12 +54,6 @@
status = "okay";
};
&pronto {
iris {
compatible = "qcom,wcn3660b";
};
};
&touchkey {
vcc-supply = <&reg_touch_key>;
vdd-supply = <&reg_touch_key>;
@ -69,6 +63,14 @@
status = "okay";
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3660b";
};
&msmgpio {
tkey_en_default: tkey-en-default-state {
pins = "gpio97";

8
arch/arm64/boot/dts/qcom/msm8916-samsung-e2015-common.dtsi
View File

@ -58,6 +58,14 @@
vdd-supply = <&reg_touch_key>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&msmgpio {
tkey_en_default: tkey-en-default-state {
pins = "gpio97";

16
arch/arm64/boot/dts/qcom/msm8916-samsung-gt5-common.dtsi
View File

@ -125,14 +125,6 @@
status = "okay";
};
&pronto {
status = "okay";
iris {
compatible = "qcom,wcn3660b";
};
};
&sdhc_1 {
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
@ -162,6 +154,14 @@
extcon = <&pm8916_usbin>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3660b";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

12
arch/arm64/boot/dts/qcom/msm8916-samsung-j5-common.dtsi
View File

@ -93,10 +93,6 @@
linux,code = <KEY_VOLUMEDOWN>;
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
@ -124,6 +120,14 @@
extcon = <&muic>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

16
arch/arm64/boot/dts/qcom/msm8916-samsung-serranove.dts
View File

@ -272,14 +272,6 @@
status = "okay";
};
&pronto {
status = "okay";
iris {
compatible = "qcom,wcn3660b";
};
};
&sdhc_1 {
status = "okay";
@ -320,6 +312,14 @@
extcon = <&muic>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3660b";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

4
arch/arm64/boot/dts/qcom/msm8916-thwc-uf896.dts
View File

@ -33,7 +33,3 @@
&gpio_leds_default {
pins = "gpio81", "gpio82", "gpio83";
};
&sim_ctrl_default {
pins = "gpio1", "gpio2";
};

28
arch/arm64/boot/dts/qcom/msm8916-thwc-ufi001c.dts
View File

@ -25,6 +25,11 @@
gpios = <&msmgpio 20 GPIO_ACTIVE_HIGH>;
};
&mpss {
pinctrl-0 = <&sim_ctrl_default>;
pinctrl-names = "default";
};
&button_default {
pins = "gpio37";
bias-pull-down;
@ -34,6 +39,25 @@
pins = "gpio20", "gpio21", "gpio22";
};
&sim_ctrl_default {
pins = "gpio1", "gpio2";
/* This selects the external SIM card slot by default */
&msmgpio {
sim_ctrl_default: sim-ctrl-default-state {
esim-sel-pins {
pins = "gpio0", "gpio3";
bias-disable;
output-low;
};
sim-en-pins {
pins = "gpio1";
bias-disable;
output-low;
};
sim-sel-pins {
pins = "gpio2";
bias-disable;
output-high;
};
};
};

22
arch/arm64/boot/dts/qcom/msm8916-ufi.dtsi
View File

@ -92,9 +92,6 @@
};
&mpss {
pinctrl-0 = <&sim_ctrl_default>;
pinctrl-names = "default";
status = "okay";
};
@ -102,10 +99,6 @@
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>;
pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off>;
@ -125,6 +118,14 @@
extcon = <&pm8916_usbin>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;
@ -240,11 +241,4 @@
drive-strength = <2>;
bias-disable;
};
sim_ctrl_default: sim-ctrl-default-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
output-low;
};
};

12
arch/arm64/boot/dts/qcom/msm8916-wingtech-wt88047.dts
View File

@ -153,10 +153,6 @@
status = "okay";
};
&pronto {
status = "okay";
};
&sdhc_1 {
status = "okay";
@ -184,6 +180,14 @@
extcon = <&usb_id>;
};
&wcnss {
status = "okay";
};
&wcnss_iris {
compatible = "qcom,wcn3620";
};
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l4_l5_l6-supply = <&pm8916_s4>;

35
arch/arm64/boot/dts/qcom/msm8916-yiming-uz801v3.dts Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0-only
/dts-v1/;
#include "msm8916-ufi.dtsi"
/ {
model = "uz801 v3.0 4G Modem Stick";
compatible = "yiming,uz801-v3", "qcom,msm8916";
};
&button_restart {
gpios = <&msmgpio 23 GPIO_ACTIVE_LOW>;
};
&led_r {
gpios = <&msmgpio 7 GPIO_ACTIVE_HIGH>;
};
&led_g {
gpios = <&msmgpio 8 GPIO_ACTIVE_HIGH>;
};
&led_b {
gpios = <&msmgpio 6 GPIO_ACTIVE_HIGH>;
};
&button_default {
pins = "gpio23";
bias-pull-up;
};
&gpio_leds_default {
pins = "gpio6", "gpio7", "gpio8";
};

16
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@ -503,7 +503,7 @@
bits = <1 7>;
};
tsens_mode: mode@ec {
tsens_mode: mode@ef {
reg = <0xef 0x1>;
bits = <5 3>;
};
@ -1870,7 +1870,7 @@
};
};
pronto: remoteproc@a21b000 {
wcnss: remoteproc@a21b000 {
compatible = "qcom,pronto-v2-pil", "qcom,pronto";
reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>;
reg-names = "ccu", "dxe", "pmu";
@ -1896,9 +1896,8 @@
status = "disabled";
iris {
compatible = "qcom,wcn3620";
wcnss_iris: iris {
/* Separate chip, compatible is board-specific */
clocks = <&rpmcc RPM_SMD_RF_CLK2>;
clock-names = "xo";
};
@ -1916,13 +1915,13 @@
compatible = "qcom,wcnss";
qcom,smd-channels = "WCNSS_CTRL";
qcom,mmio = <&pronto>;
qcom,mmio = <&wcnss>;
bluetooth {
wcnss_bt: bluetooth {
compatible = "qcom,wcnss-bt";
};
wifi {
wcnss_wifi: wifi {
compatible = "qcom,wcnss-wlan";
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
@ -2180,7 +2179,6 @@
};
};
};
};
timer {

123
arch/arm64/boot/dts/qcom/msm8953.dtsi
View File

@ -2,6 +2,7 @@
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
#include <dt-bindings/clock/qcom,gcc-msm8953.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
@ -269,7 +270,7 @@
compatible = "qcom,rpm-msm8953";
qcom,smd-channels = "rpm_requests";
rpmcc: rpmcc {
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
@ -281,9 +282,6 @@
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
clocks = <&xo_board>;
clock-names = "ref";
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
@ -352,12 +350,12 @@
rpm_msg_ram: sram@60000 {
compatible = "qcom,rpm-msg-ram";
reg = <0x60000 0x8000>;
reg = <0x00060000 0x8000>;
};
hsusb_phy: phy@79000 {
compatible = "qcom,msm8953-qusb2-phy";
reg = <0x79000 0x180>;
reg = <0x00079000 0x180>;
#phy-cells = <0>;
clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>,
@ -380,8 +378,8 @@
tsens0: thermal-sensor@4a9000 {
compatible = "qcom,msm8953-tsens", "qcom,tsens-v2";
reg = <0x4a9000 0x1000>, /* TM */
<0x4a8000 0x1000>; /* SROT */
reg = <0x004a9000 0x1000>, /* TM */
<0x004a8000 0x1000>; /* SROT */
#qcom,sensors = <16>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
@ -391,12 +389,12 @@
restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>;
reg = <0x004ab000 0x4>;
};
tlmm: pinctrl@1000000 {
compatible = "qcom,msm8953-pinctrl";
reg = <0x1000000 0x300000>;
reg = <0x01000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
gpio-ranges = <&tlmm 0 0 142>;
@ -636,16 +634,16 @@
gcc: clock-controller@1800000 {
compatible = "qcom,gcc-msm8953";
reg = <0x1800000 0x80000>;
reg = <0x01800000 0x80000>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&xo_board>,
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>,
<0>,
<0>,
<0>,
<0>;
<&dsi0_phy 1>,
<&dsi0_phy 0>,
<&dsi1_phy 1>,
<&dsi1_phy 0>;
clock-names = "xo",
"sleep",
"dsi0pll",
@ -656,25 +654,25 @@
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,tcsr-mutex";
reg = <0x1905000 0x20000>;
reg = <0x01905000 0x20000>;
#hwlock-cells = <1>;
};
tcsr: syscon@1937000 {
compatible = "qcom,tcsr-msm8953", "syscon";
reg = <0x1937000 0x30000>;
reg = <0x01937000 0x30000>;
};
tcsr_phy_clk_scheme_sel: syscon@193f044 {
compatible = "qcom,tcsr-msm8953", "syscon";
reg = <0x193f044 0x4>;
reg = <0x0193f044 0x4>;
};
mdss: display-subsystem@1a00000 {
compatible = "qcom,mdss";
reg = <0x1a00000 0x1000>,
<0x1ab0000 0x1040>;
reg = <0x01a00000 0x1000>,
<0x01ab0000 0x1040>;
reg-names = "mdss_phys",
"vbif_phys";
@ -701,7 +699,7 @@
mdp: display-controller@1a01000 {
compatible = "qcom,msm8953-mdp5", "qcom,mdp5";
reg = <0x1a01000 0x89000>;
reg = <0x01a01000 0x89000>;
reg-names = "mdp_phys";
interrupt-parent = <&mdss>;
@ -742,7 +740,7 @@
dsi0: dsi@1a94000 {
compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x1a94000 0x400>;
reg = <0x01a94000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
@ -794,9 +792,9 @@
dsi0_phy: phy@1a94400 {
compatible = "qcom,dsi-phy-14nm-8953";
reg = <0x1a94400 0x100>,
<0x1a94500 0x300>,
<0x1a94800 0x188>;
reg = <0x01a94400 0x100>,
<0x01a94500 0x300>,
<0x01a94800 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
@ -804,7 +802,7 @@
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
@ -812,7 +810,7 @@
dsi1: dsi@1a96000 {
compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x1a96000 0x400>;
reg = <0x01a96000 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
@ -861,9 +859,9 @@
dsi1_phy: phy@1a96400 {
compatible = "qcom,dsi-phy-14nm-8953";
reg = <0x1a96400 0x100>,
<0x1a96500 0x300>,
<0x1a96800 0x188>;
reg = <0x01a96400 0x100>,
<0x01a96500 0x300>,
<0x01a96800 0x188>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
@ -871,7 +869,7 @@
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&xo_board>;
clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "ref";
status = "disabled";
@ -880,7 +878,7 @@
apps_iommu: iommu@1e00000 {
compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1";
ranges = <0 0x1e20000 0x20000>;
ranges = <0 0x01e20000 0x20000>;
clocks = <&gcc GCC_SMMU_CFG_CLK>,
<&gcc GCC_APSS_TCU_ASYNC_CLK>;
@ -916,11 +914,11 @@
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f000 0x1000>,
<0x2400000 0x800000>,
<0x2c00000 0x800000>,
<0x3800000 0x200000>,
<0x200a000 0x2100>;
reg = <0x0200f000 0x1000>,
<0x02400000 0x800000>,
<0x02c00000 0x800000>,
<0x03800000 0x200000>,
<0x0200a000 0x2100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
@ -935,7 +933,7 @@
usb3: usb@70f8800 {
compatible = "qcom,msm8953-dwc3", "qcom,dwc3";
reg = <0x70f8800 0x400>;
reg = <0x070f8800 0x400>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
@ -979,14 +977,13 @@
snps,hird-threshold = /bits/ 8 <0x00>;
maximum-speed = "high-speed";
phy_mode = "utmi";
};
};
sdhc_1: mmc@7824900 {
compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
reg = <0x7824900 0x500>, <0x7824000 0x800>;
reg = <0x07824900 0x500>, <0x07824000 0x800>;
reg-names = "hc", "core";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
@ -995,7 +992,7 @@
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
power-domains = <&rpmpd MSM8953_VDDCX>;
@ -1046,7 +1043,7 @@
sdhc_2: mmc@7864900 {
compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4";
reg = <0x7864900 0x500>, <0x7864000 0x800>;
reg = <0x07864900 0x500>, <0x07864000 0x800>;
reg-names = "hc", "core";
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
@ -1055,7 +1052,7 @@
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface", "core", "xo";
power-domains = <&rpmpd MSM8953_VDDCX>;
@ -1101,7 +1098,7 @@
uart_0: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
reg = <0x078af000 0x200>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@ -1112,7 +1109,7 @@
i2c_1: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b5000 0x600>;
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
@ -1130,7 +1127,7 @@
i2c_2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b6000 0x600>;
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
@ -1148,7 +1145,7 @@
i2c_3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
@ -1165,7 +1162,7 @@
i2c_4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b8000 0x600>;
reg = <0x078b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
@ -1182,7 +1179,7 @@
i2c_5: i2c@7af5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af5000 0x600>;
reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
@ -1199,7 +1196,7 @@
i2c_6: i2c@7af6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af6000 0x600>;
reg = <0x07af6000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
@ -1216,7 +1213,7 @@
i2c_7: i2c@7af7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af7000 0x600>;
reg = <0x07af7000 0x600>;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
@ -1233,7 +1230,7 @@
i2c_8: i2c@7af8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af8000 0x600>;
reg = <0x07af8000 0x600>;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
@ -1257,13 +1254,13 @@
apcs: mailbox@b011000 {
compatible = "qcom,msm8953-apcs-kpss-global", "syscon";
reg = <0xb011000 0x1000>;
reg = <0x0b011000 0x1000>;
#mbox-cells = <1>;
};
timer@b120000 {
compatible = "arm,armv7-timer-mem";
reg = <0xb120000 0x1000>;
reg = <0x0b120000 0x1000>;
#address-cells = <0x01>;
#size-cells = <0x01>;
ranges;
@ -1272,49 +1269,49 @@
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb121000 0x1000>,
<0xb122000 0x1000>;
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
};
frame@b123000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb123000 0x1000>;
reg = <0x0b123000 0x1000>;
status = "disabled";
};
frame@b124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb124000 0x1000>;
reg = <0x0b124000 0x1000>;
status = "disabled";
};
frame@b125000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb125000 0x1000>;
reg = <0x0b125000 0x1000>;
status = "disabled";
};
frame@b126000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb126000 0x1000>;
reg = <0x0b126000 0x1000>;
status = "disabled";
};
frame@b127000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb127000 0x1000>;
reg = <0x0b127000 0x1000>;
status = "disabled";
};
frame@b128000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xb128000 0x1000>;
reg = <0x0b128000 0x1000>;
status = "disabled";
};
};

4
arch/arm64/boot/dts/qcom/msm8956-sony-xperia-loire.dtsi
View File

@ -280,3 +280,7 @@
vdda3p3-supply = <&pm8950_l13>;
status = "okay";
};
&xo_board {
clock-frequency = <19200000>;
};

10
arch/arm64/boot/dts/qcom/msm8976.dtsi
View File

@ -20,6 +20,13 @@
chosen { };
clocks {
xo_board: xo-board {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -351,6 +358,8 @@
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
clocks = <&xo_board>;
clock-names = "xo";
#clock-cells = <1>;
};
@ -809,7 +818,6 @@
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
sdhc_1: mmc@7824000 {

5
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon.dtsi
View File

@ -46,8 +46,6 @@
};
clocks {
compatible = "simple-bus";
divclk4: divclk4 {
compatible = "fixed-clock";
#clock-cells = <0>;
@ -542,8 +540,7 @@
};
&pmi8994_spmi_regulators {
vdd_gfx: s2@1700 {
reg = <0x1700 0x100>;
vdd_gfx: s2 {
regulator-min-microvolt = <980000>;
regulator-max-microvolt = <980000>;
};

3
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami.dtsi
View File

@ -173,8 +173,7 @@
* power domain.. which still isn't enough and forces us to bind
* OXILI_CX and OXILI_GX together!
*/
vdd_gfx: s2@1700 {
reg = <0x1700 0x100>;
vdd_gfx: s2 {
regulator-name = "VDD_GFX";
regulator-min-microvolt = <980000>;
regulator-max-microvolt = <980000>;

2
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@ -242,7 +242,7 @@
compatible = "qcom,rpm-msm8994";
qcom,smd-channels = "rpm_requests";
rpmcc: rpmcc {
rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc";
#clock-cells = <1>;
};

67
arch/arm64/boot/dts/qcom/msm8996-oneplus-common.dtsi
View File

@ -85,10 +85,6 @@
};
};
&adsp_pil {
status = "okay";
};
&blsp1_i2c3 {
status = "okay";
@ -183,10 +179,6 @@
status = "okay";
};
&gpu {
status = "okay";
};
&hsusb_phy1 {
vdd-supply = <&vreg_l28a_0p925>;
vdda-pll-supply = <&vreg_l12a_1p8>;
@ -215,7 +207,6 @@
&mss_pil {
pll-supply = <&vreg_l12a_1p8>;
status = "okay";
};
&pcie0 {
@ -504,8 +495,48 @@
};
};
&slpi_pil {
&slim_msm {
status = "okay";
slim@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
tasha_ifd: tas-ifd@0,0 {
compatible = "slim217,1a0";
reg = <0 0>;
};
wcd9335: codec@1,0 {
compatible = "slim217,1a0";
reg = <1 0>;
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
<&rpmcc RPM_SMD_BB_CLK1>;
interrupt-parent = <&tlmm>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
pinctrl-names = "default";
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
slim-ifc-dev = <&tasha_ifd>;
#sound-dai-cells = <1>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
};
};
};
&sound {
@ -768,19 +799,3 @@
maximum-speed = "high-speed";
};
&venus {
status = "okay";
};
&wcd9335 {
clock-names = "mclk", "slimbus";
clocks = <&div1_mclk>,
<&rpmcc RPM_SMD_BB_CLK1>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
};

6
arch/arm64/boot/dts/qcom/msm8996-oneplus3.dts
View File

@ -17,6 +17,7 @@
&adsp_pil {
firmware-name = "qcom/msm8996/oneplus3/adsp.mbn";
status = "okay";
};
&battery {
@ -25,6 +26,8 @@
};
&gpu {
status = "okay";
zap-shader {
firmware-name = "qcom/msm8996/oneplus3/a530_zap.mbn";
};
@ -33,12 +36,15 @@
&mss_pil {
firmware-name = "qcom/msm8996/oneplus3/mba.mbn",
"qcom/msm8996/oneplus3/modem.mbn";
status = "okay";
};
&slpi_pil {
firmware-name = "qcom/msm8996/oneplus3/slpi.mbn";
status = "okay";
};
&venus {
firmware-name = "qcom/msm8996/oneplus3/venus.mbn";
status = "okay";
};

6
arch/arm64/boot/dts/qcom/msm8996-oneplus3t.dts
View File

@ -18,6 +18,7 @@
&adsp_pil {
firmware-name = "qcom/msm8996/oneplus3t/adsp.mbn";
status = "okay";
};
&battery {
@ -26,6 +27,8 @@
};
&gpu {
status = "okay";
zap-shader {
firmware-name = "qcom/msm8996/oneplus3t/a530_zap.mbn";
};
@ -34,12 +37,15 @@
&mss_pil {
firmware-name = "qcom/msm8996/oneplus3t/mba.mbn",
"qcom/msm8996/oneplus3t/modem.mbn";
status = "okay";
};
&slpi_pil {
firmware-name = "qcom/msm8996/oneplus3t/slpi.mbn";
status = "okay";
};
&venus {
firmware-name = "qcom/msm8996/oneplus3t/venus.mbn";
status = "okay";
};

62
arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi
View File

@ -12,8 +12,6 @@
/ {
clocks {
compatible = "simple-bus";
divclk1_cdc: divclk1 {
compatible = "gpio-gate-clock";
clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
@ -337,6 +335,52 @@
};
};
&slim_msm {
status = "okay";
slim@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
tasha_ifd: tas-ifd@0,0 {
compatible = "slim217,1a0";
reg = <0 0>;
};
wcd9335: codec@1,0 {
compatible = "slim217,1a0";
reg = <1 0>;
clock-names = "mclk", "slimbus";
clocks = <&divclk1_cdc>,
<&rpmcc RPM_SMD_BB_CLK1>;
interrupt-parent = <&tlmm>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
pinctrl-names = "default";
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
slim-ifc-dev = <&tasha_ifd>;
#sound-dai-cells = <1>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-vbat-supply = <&vph_pwr>;
vdd-micbias-supply = <&vph_pwr_bbyp>;
vdd-io-supply = <&vreg_s4a_1p8>;
};
};
};
&slpi_pil {
status = "okay";
@ -395,20 +439,6 @@
status = "okay";
};
&wcd9335 {
clock-names = "mclk", "slimbus";
clocks = <&divclk1_cdc>,
<&rpmcc RPM_SMD_BB_CLK1>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-vbat-supply = <&vph_pwr>;
vdd-micbias-supply = <&vph_pwr_bbyp>;
vdd-io-supply = <&vreg_s4a_1p8>;
};
&rpm_requests {
regulators-0 {
compatible = "qcom,rpm-pm8994-regulators";

47
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -1851,8 +1851,8 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
ranges = <0x01000000 0x0 0x00000000 0x0c200000 0x0 0x100000>,
<0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
device_type = "pci";
@ -1882,7 +1882,6 @@
"cfg",
"bus_master",
"bus_slave";
};
pcie1: pcie@608000 {
@ -1905,8 +1904,8 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
ranges = <0x01000000 0x0 0x00000000 0x0d200000 0x0 0x100000>,
<0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
device_type = "pci";
@ -1956,8 +1955,8 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
ranges = <0x01000000 0x0 0x00000000 0x0e200000 0x0 0x100000>,
<0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
device_type = "pci";
@ -3006,8 +3005,11 @@
interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
phys = <&hsusb_phy1>, <&ssusb_phy_0>;
phy-names = "usb2-phy", "usb3-phy";
snps,hird-threshold = /bits/ 8 <0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,is-utmi-l1-suspend;
tx-fifo-resize;
};
};
@ -3383,36 +3385,8 @@
dma-names = "rx", "tx";
#address-cells = <1>;
#size-cells = <0>;
slim@1 {
reg = <1>;
#address-cells = <2>;
#size-cells = <0>;
tasha_ifd: tas-ifd@0,0 {
compatible = "slim217,1a0";
reg = <0 0>;
};
wcd9335: codec@1,0 {
pinctrl-0 = <&cdc_reset_active &wcd_intr_default>;
pinctrl-names = "default";
compatible = "slim217,1a0";
reg = <1 0>;
interrupt-parent = <&tlmm>;
interrupts = <54 IRQ_TYPE_LEVEL_HIGH>,
<53 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr1", "intr2";
interrupt-controller;
#interrupt-cells = <1>;
reset-gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
slim-ifc-dev = <&tasha_ifd>;
#sound-dai-cells = <1>;
};
};
status = "disabled";
};
adsp_pil: remoteproc@9300000 {
@ -3496,7 +3470,6 @@
};
};
};
};
};

4
arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts
View File

@ -44,7 +44,7 @@
label = "Keyboard Hall Sensor";
gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>;
debounce-interval = <15>;
gpio-key,wakeup;
wakeup-source;
linux,input-type = <EV_SW>;
linux,code = <SW_KEYPAD_SLIDE>;
};
@ -116,7 +116,7 @@
gpios = <&pm8998_gpios 6 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
wakeup-source;
debounce-interval = <15>;
};

2
arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
View File

@ -34,7 +34,7 @@
&pmi8998_gpios {
button_backlight_default: button-backlight-state {
pins = "gpio5";
function = "gpio";
function = "normal";
bias-pull-down;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};

179
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts
View File

@ -22,7 +22,7 @@
enable-active-high;
gpio = <&pmi8998_gpios 10 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&disp_dvdd_en>;
pinctrl-0 = <&four_k_disp_dcdc_en>;
};
};
@ -37,8 +37,30 @@
qcom,soft-start-us = <200>;
};
&pm8005_gpios {
gpio-line-names = "EAR_EN", /* GPIO_1 */
"NC",
"SLB",
"OPTION_1_PM8005";
};
&pmi8998_gpios {
disp_dvdd_en: disp-dvdd-en-active-state {
gpio-line-names = "MAIN_CAM_PWR_IO_EN", /* GPIO_1 */
"NC",
"NC",
"TYPEC_UUSB_SEL",
"VIB_LDO_EN",
"NC",
"DISPLAY_TYPE_SEL",
"USB_SWITCH_SEL",
"NC",
"4K_DISP_DCDC_EN", /* GPIO_10 */
"NC",
"DIV_CLK3",
"SPMI_I2C_SEL",
"NC";
four_k_disp_dcdc_en: 4k-disp-dcdc-en-state {
pins = "gpio10";
function = "normal";
bias-disable;
@ -49,6 +71,159 @@
};
};
&tlmm {
gpio-line-names = "", /* GPIO_0 */
"",
"",
"",
"DEBUG_UART_TX",
"DEBUG_UART_RX",
"CAMSENSOR_I2C_SDA",
"CAMSENSOR_I2C_SCL",
"NC",
"NC",
"MDP_VSYNC_P", /* GPIO_10 */
"RGBC_IR_INT",
"NFC_VEN",
"CAM_MCLK0",
"CAM_MCLK1",
"NC",
"NC",
"CCI_I2C_SDA0",
"CCI_I2C_SCL0",
"CCI_I2C_SDA1",
"CCI_I2C_SCL1", /* GPIO_20 */
"MAIN_CAM_PWR_EN",
"TOF_INT_N",
"NC",
"NC",
"CHAT_CAM_PWR_EN",
"NC",
"TOF_RESET_N",
"CAM2_RSTN",
"NC",
"CAM1_RSTN", /* GPIO_30 */
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"CC_DIR",
"UIM2_DETECT_EN",
"FP_RESET_N", /* GPIO_40 */
"NC",
"NC",
"NC",
"NC",
"BT_HCI_UART_TXD",
"BT_HCI_UART_RXD",
"BT_HCI_UART_CTS_N",
"BT_HCI_UART_RFR_N",
"NC",
"NC", /* GPIO_50 */
"NC",
"NC",
"CODEC_INT2_N",
"CODEC_INT1_N",
"APPS_I2C_SDA",
"APPS_I2C_SCL",
"FORCED_USB_BOOT",
"NC",
"NC",
"NC", /* GPIO_60 */
"NC",
"NC",
"TRAY2_DET_DS",
"CODEC_RST_N",
"WSA_L_EN",
"WSA_R_EN",
"NC",
"NC",
"NC",
"LPASS_SLIMBUS_CLK", /* GPIO_70 */
"LPASS_SLIMBUS_DATA0",
"LPASS_SLIMBUS_DATA1",
"BT_FM_SLIMBUS_DATA",
"BT_FM_SLIMBUS_CLK",
"NC",
"RF_LCD_ID_EN",
"NC",
"NC",
"NC",
"NC", /* GPIO_80 */
"SW_SERVICE",
"TX_GTR_THRES_IN",
"HW_ID0",
"HW_ID1",
"NC",
"NC",
"TS_I2C_SDA",
"TS_I2C_SCL",
"TS_RESET_N",
"NC", /* GPIO_90 */
"NC",
"NFC_IRQ",
"NFC_DWLD_EN",
"DISP_RESET_N",
"TRAY2_DET",
"CAM_SOF",
"RFFE6_CLK",
"RFFE6_DATA",
"DEBUG_GPIO0",
"DEBUG_GPIO1", /* GPIO_100 */
"GRFC4",
"NC",
"NC",
"RSVD",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RESET",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK", /* GPIO_110 */
"UIM1_RST",
"UIM1_PRESENT",
"UIM_BATT_ALARM",
"RSVD",
"NC",
"NC",
"ACCEL_INT",
"GYRO_INT",
"COMPASS_INT",
"ALS_PROX_INT_N", /* GPIO_120 */
"FP_INT_N",
"NC",
"BAROMETER_INT",
"ACC_COVER_OPEN",
"TS_INT_N",
"NC",
"NC",
"USB_DETECT_EN",
"NC",
"QLINK_REQUEST", /* GPIO_130 */
"QLINK_ENABLE",
"NC",
"TS_VDDIO_EN",
"WMSS_RESET_N",
"PA_INDICATOR_OR",
"NC",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK", /* GPIO_140 */
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"MSS_LTE_COXM_TXD",
"MSS_LTE_COXM_RXD",
"RFFE2_DATA",
"RFFE2_CLK",
"RFFE1_DATA",
"RFFE1_CLK";
};
&vreg_l22a_2p85 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;

264
arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi
View File

@ -21,7 +21,7 @@
clocks {
div1_mclk: divclk1 {
compatible = "gpio-gate-clock";
pinctrl-0 = <&audio_mclk_pin>;
pinctrl-0 = <&div_clk1>;
pinctrl-names = "default";
clocks = <&rpmcc RPM_SMD_DIV_CLK1>;
#clock-cells = <0>;
@ -46,7 +46,7 @@
enable-active-high;
gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam0_vdig_default>;
pinctrl-0 = <&main_cam_pwr_en>;
};
cam1_vdig_vreg: cam1-vdig {
@ -56,7 +56,7 @@
enable-active-high;
gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam1_vdig_default>;
pinctrl-0 = <&chat_cam_pwr_en>;
vin-supply = <&vreg_s3a_1p35>;
};
@ -67,7 +67,7 @@
enable-active-high;
gpio = <&pmi8998_gpios 1 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&cam_vio_default>;
pinctrl-0 = <&main_cam_pwr_io_en>;
vin-supply = <&vreg_lvs1a_1p8>;
};
@ -92,21 +92,20 @@
id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>;
vbus-gpio = <&tlmm 128 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&usb_extcon_active &usb_vbus_active>;
pinctrl-0 = <&cc_dir_default &usb_detect_en>;
};
gpio-keys {
compatible = "gpio-keys";
label = "Side buttons";
pinctrl-names = "default";
pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>,
<&cam_snapshot_pin_a>;
pinctrl-0 = <&vol_down_n &focus_n &snapshot_n>;
button-vol-down {
label = "Volume Down";
gpios = <&pm8998_gpios 5 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_KEY>;
linux,code = <KEY_VOLUMEDOWN>;
gpio-key,wakeup;
wakeup-source;
debounce-interval = <15>;
};
@ -131,14 +130,14 @@
compatible = "gpio-keys";
label = "Hall sensors";
pinctrl-names = "default";
pinctrl-0 = <&hall_sensor0_default>;
pinctrl-0 = <&acc_cover_open>;
event-hall-sensor0 {
label = "Cover Hall Sensor";
gpios = <&tlmm 124 GPIO_ACTIVE_LOW>;
linux,input-type = <EV_SW>;
linux,code = <SW_LID>;
gpio-key,wakeup;
wakeup-source;
debounce-interval = <30>;
};
};
@ -189,7 +188,7 @@
compatible = "gpio-vibrator";
enable-gpios = <&pmi8998_gpios 5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vib_default>;
pinctrl-0 = <&vib_ldo_en>;
};
};
@ -263,7 +262,7 @@
vdd-supply = <&cam_vio_vreg>;
pinctrl-names = "default";
pinctrl-0 = <&tof_int &tof_reset>;
pinctrl-0 = <&tof_int_n &tof_reset>;
};
};
@ -292,6 +291,13 @@
regulator-soft-start;
};
&pm8005_gpios {
gpio-line-names = "NC", /* GPIO_1 */
"NC",
"SLB",
"OPTION_1_PM8005";
};
&pm8005_regulators {
/* VDD_GFX supply */
pm8005_s1: s1 {
@ -304,7 +310,34 @@
};
&pm8998_gpios {
vol_down_pin_a: vol-down-active-state {
gpio-line-names = "UIM_BATT_ALARM", /* GPIO_1 */
"NC",
"WLAN_SW_CTRL (DISALLOWED)",
"SSC_PWR_EN",
"VOL_DOWN_N",
"VOL_UP_N",
"SNAPSHOT_N",
"FOCUS_N",
"FLASH_THERM",
"", /* GPIO_10 */
"",
"",
"DIV_CLK1",
"NC",
"NC (DISALLOWED)",
"DIV_CLK3",
"NC",
"NC",
"NC",
"NC (DISALLOWED)", /* GPIO_20 */
"NFC_CLK_REQ",
"NC (DISALLOWED)",
"WCSS_PWR_REQ",
"OPTION_1 (DISALLOWED)",
"OPTION_2 (DISALLOWED)",
"PM_SLB (DISALLOWED)";
vol_down_n: vol-down-n-state {
pins = "gpio5";
function = PMIC_GPIO_FUNC_NORMAL;
bias-pull-up;
@ -312,7 +345,7 @@
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
cam_focus_pin_a: cam-focus-btn-active-state {
focus_n: focus-n-state {
pins = "gpio7";
function = PMIC_GPIO_FUNC_NORMAL;
bias-pull-up;
@ -320,7 +353,7 @@
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
cam_snapshot_pin_a: cam-snapshot-btn-active-state {
snapshot_n: snapshot-n-state {
pins = "gpio8";
function = PMIC_GPIO_FUNC_NORMAL;
bias-pull-up;
@ -328,7 +361,7 @@
qcom,drive-strength = <PMIC_GPIO_STRENGTH_NO>;
};
audio_mclk_pin: audio-mclk-pin-active-state {
div_clk1: div-clk1-state {
pins = "gpio13";
function = "func2";
power-source = <0>;
@ -336,7 +369,22 @@
};
&pmi8998_gpios {
cam_vio_default: cam-vio-active-state {
gpio-line-names = "MAIN_CAM_PWR_IO_EN", /* GPIO_1 */
"NC",
"NC",
"TYPEC_UUSB_SEL",
"VIB_LDO_EN",
"NC",
"DISPLAY_TYPE_SEL",
"NC",
"NC",
"NC", /* GPIO_10 */
"NC",
"DIV_CLK3",
"SPMI_I2C_SEL",
"NC";
main_cam_pwr_io_en: main-cam-pwr-io-en-state {
pins = "gpio1";
function = PMIC_GPIO_FUNC_NORMAL;
bias-disable;
@ -346,7 +394,7 @@
power-source = <1>;
};
vib_default: vib-en-state {
vib_ldo_en: vib-ldo-en-state {
pins = "gpio5";
function = PMIC_GPIO_FUNC_NORMAL;
bias-disable;
@ -590,8 +638,158 @@
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
gpio-line-names = "", /* GPIO_0 */
"",
"",
"",
"DEBUG_UART_TX",
"DEBUG_UART_RX",
"CAMSENSOR_I2C_SDA",
"CAMSENSOR_I2C_SCL",
"NC",
"NC",
"MDP_VSYNC_P", /* GPIO_10 */
"RGBC_IR_INT",
"NFC_VEN",
"CAM_MCLK0",
"CAM_MCLK1",
"NC",
"NC",
"CCI_I2C_SDA0",
"CCI_I2C_SCL0",
"CCI_I2C_SDA1",
"CCI_I2C_SCL1", /* GPIO_20 */
"MAIN_CAM_PWR_EN",
"TOF_INT_N",
"NC",
"NC",
"CHAT_CAM_PWR_EN",
"NC",
"TOF_RESET_N",
"CAM2_RSTN",
"NC",
"CAM1_RSTN", /* GPIO_30 */
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"CC_DIR",
"UIM2_DETECT_EN",
"FP_RESET_N", /* GPIO_40 */
"NC",
"NC",
"NC",
"NC",
"BT_HCI_UART_TXD",
"BT_HCI_UART_RXD",
"BT_HCI_UART_CTS_N",
"BT_HCI_UART_RFR_N",
"NC",
"NC", /* GPIO_50 */
"NC",
"NC",
"CODEC_INT2_N",
"CODEC_INT1_N",
"APPS_I2C_SDA",
"APPS_I2C_SCL",
"FORCED_USB_BOOT",
"NC",
"NC",
"NC", /* GPIO_60 */
"NC",
"NC",
"TRAY2_DET_DS",
"CODEC_RST_N",
"WSA_L_EN",
"WSA_R_EN",
"NC",
"NC",
"NC",
"LPASS_SLIMBUS_CLK", /* GPIO_70 */
"LPASS_SLIMBUS_DATA0",
"LPASS_SLIMBUS_DATA1",
"BT_FM_SLIMBUS_DATA",
"BT_FM_SLIMBUS_CLK",
"NC",
"RF_LCD_ID_EN",
"NC",
"NC",
"NC",
"NC", /* GPIO_80 */
"SW_SERVICE",
"TX_GTR_THRES_IN",
"HW_ID0",
"HW_ID1",
"NC",
"NC",
"TS_I2C_SDA",
"TS_I2C_SCL",
"TS_RESET_N",
"NC", /* GPIO_90 */
"NC",
"NFC_IRQ",
"NFC_DWLD_EN",
"DISP_RESET_N",
"TRAY2_DET",
"CAM_SOF",
"RFFE6_CLK",
"RFFE6_DATA",
"DEBUG_GPIO0",
"DEBUG_GPIO1", /* GPIO_100 */
"GRFC4",
"NC",
"NC",
"RSVD",
"UIM2_DATA",
"UIM2_CLK",
"UIM2_RESET",
"UIM2_PRESENT",
"UIM1_DATA",
"UIM1_CLK", /* GPIO_110 */
"UIM1_RST",
"UIM1_PRESENT",
"UIM_BATT_ALARM",
"RSVD",
"NC",
"NC",
"ACCEL_INT",
"GYRO_INT",
"COMPASS_INT",
"ALS_PROX_INT_N", /* GPIO_120 */
"FP_INT_N",
"NC",
"BAROMETER_INT",
"ACC_COVER_OPEN",
"TS_INT_N",
"NC",
"NC",
"USB_DETECT_EN",
"NC",
"QLINK_REQUEST", /* GPIO_130 */
"QLINK_ENABLE",
"NC",
"NC",
"WMSS_RESET_N",
"PA_INDICATOR_OR",
"NC",
"RFFE3_DATA",
"RFFE3_CLK",
"RFFE4_DATA",
"RFFE4_CLK", /* GPIO_140 */
"RFFE5_DATA",
"RFFE5_CLK",
"GNSS_EN",
"MSS_LTE_COXM_TXD",
"MSS_LTE_COXM_RXD",
"RFFE2_DATA",
"RFFE2_CLK",
"RFFE1_DATA",
"RFFE1_CLK";
mdp_vsync_n: mdp-vsync-n-state {
mdp_vsync_p: mdp-vsync-p-state {
pins = "gpio10";
function = "mdp_vsync_a";
drive-strength = <2>;
@ -606,14 +804,14 @@
output-low;
};
msm_mclk0_default: msm-mclk0-active-state {
cam_mclk0_active: cam-mclk0-active-state {
pins = "gpio13";
function = "cam_mclk";
drive-strength = <2>;
bias-disable;
};
msm_mclk1_default: msm-mclk1-active-state {
cam_mclk1_active: cam-mclk1-active-state {
pins = "gpio14";
function = "cam_mclk";
drive-strength = <2>;
@ -634,14 +832,14 @@
drive-strength = <2>;
};
cam0_vdig_default: cam0-vdig-default-state {
main_cam_pwr_en: main-cam-pwr-en-default-state {
pins = "gpio21";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
tof_int: tof-int-state {
tof_int_n: tof-int-n-state {
pins = "gpio22";
function = "gpio";
bias-pull-up;
@ -649,20 +847,13 @@
input-enable;
};
cam1_vdig_default: cam1-vdig-default-state {
chat_cam_pwr_en: chat-cam-pwr-en-default-state {
pins = "gpio25";
function = "gpio";
bias-disable;
drive-strength = <2>;
};
usb_extcon_active: usb-extcon-active-state {
pins = "gpio38";
function = "gpio";
bias-disable;
drive-strength = <16>;
};
tof_reset: tof-reset-state {
pins = "gpio27";
function = "gpio";
@ -670,7 +861,14 @@
drive-strength = <2>;
};
hall_sensor0_default: acc-cover-open-state {
cc_dir_default: cc-dir-active-state {
pins = "gpio38";
function = "gpio";
bias-disable;
drive-strength = <16>;
};
acc_cover_open: acc-cover-open-state {
pins = "gpio124";
function = "gpio";
bias-disable;
@ -685,7 +883,7 @@
bias-pull-up;
};
usb_vbus_active: usb-vbus-active-state {
usb_detect_en: usb-detect-en-active-state {
pins = "gpio128";
function = "gpio";
bias-disable;

5
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@ -922,7 +922,7 @@
phy-names = "pciephy";
status = "disabled";
ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>,
<0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
#interrupt-cells = <1>;
@ -1524,7 +1524,7 @@
compatible = "arm,coresight-stm", "arm,primecell";
reg = <0x06002000 0x1000>,
<0x16280000 0x180000>;
reg-names = "stm-base", "stm-data-base";
reg-names = "stm-base", "stm-stimulus-base";
status = "disabled";
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
@ -1993,7 +1993,6 @@
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
usb3: usb@a8f8800 {

2
arch/arm64/boot/dts/qcom/pm660.dtsi
View File

@ -11,7 +11,7 @@
/ {
thermal-zones {
pm660 {
pm660-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

2
arch/arm64/boot/dts/qcom/pm660l.dtsi
View File

@ -11,7 +11,7 @@
/ {
thermal-zones {
pm660l {
pm660l-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

6
arch/arm64/boot/dts/qcom/pm8150l.dtsi
View File

@ -116,6 +116,12 @@
#address-cells = <1>;
#size-cells = <0>;
pm8150l_flash: led-controller@d300 {
compatible = "qcom,pm8150l-flash-led", "qcom,spmi-flash-led";
reg = <0xd300>;
status = "disabled";
};
pm8150l_lpg: pwm {
compatible = "qcom,pm8150l-lpg";

6
arch/arm64/boot/dts/qcom/pm8550b.dtsi
View File

@ -55,5 +55,11 @@
interrupt-controller;
#interrupt-cells = <2>;
};
pm8550b_eusb2_repeater: phy@fd00 {
compatible = "qcom,pm8550b-eusb2-repeater";
reg = <0xfd00>;
#phy-cells = <0>;
};
};
};

2
arch/arm64/boot/dts/qcom/pm8998.dtsi
View File

@ -72,7 +72,7 @@
};
pm8998_coincell: charger@2800 {
compatible = "qcom,pm8941-coincell";
compatible = "qcom,pm8998-coincell", "qcom,pm8941-coincell";
reg = <0x2800>;
status = "disabled";

2
arch/arm64/boot/dts/qcom/pmi8994.dtsi
View File

@ -49,8 +49,6 @@
pmi8994_spmi_regulators: regulators {
compatible = "qcom,pmi8994-regulators";
#address-cells = <1>;
#size-cells = <1>;
};
pmi8994_wled: wled@d800 {

4
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@ -1469,8 +1469,8 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x81000000 0 0 0x10003000 0 0x00010000>, /* I/O */
<0x82000000 0 0x10013000 0x10013000 0 0x007ed000>; /* memory */
ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */
<0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";

21
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View File

@ -27,6 +27,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
@ -45,6 +46,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
@ -60,6 +62,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
@ -75,6 +78,7 @@
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
@ -412,8 +416,6 @@
pinctrl-0 = <&qup_uart0_default>;
pinctrl-names = "default";
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
@ -581,8 +583,6 @@
pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>;
pinctrl-names = "default";
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
@ -1312,6 +1312,7 @@
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
#clock-cells = <1>;
};
gem_noc: interconnect@19100000 {
@ -1320,6 +1321,18 @@
qcom,bcm-voters = <&apps_bcm_voter>;
#interconnect-cells = <2>;
};
system-cache-controller@19200000 {
compatible = "qcom,qdu1000-llcc";
reg = <0 0x19200000 0 0xd80000>,
<0 0x1a200000 0 0x80000>,
<0 0x221c8128 0 0x4>;
reg-names = "llcc_base",
"llcc_broadcast_base",
"multi_channel_register";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
multi-ch-bit-off = <24 2>;
};
};
timer {

4
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View File

@ -1012,7 +1012,7 @@
left_spkr: speaker@0,3 {
compatible = "sdw10217211000";
reg = <0 3>;
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrLeft";
#sound-dai-cells = <0>;
@ -1021,7 +1021,7 @@
right_spkr: speaker@0,4 {
compatible = "sdw10217211000";
reg = <0 4>;
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_HIGH>;
powerdown-gpios = <&tlmm 130 GPIO_ACTIVE_LOW>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrRight";
#sound-dai-cells = <0>;

5
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
View File

@ -17,6 +17,7 @@
aliases {
serial0 = &uart2;
serial1 = &uart9;
};
chosen {
@ -400,6 +401,10 @@
status = "okay";
};
&uart9 {
status = "okay";
};
&ufs_mem_hc {
status = "okay";

2
arch/arm64/boot/dts/qcom/sa8540p-ride.dts
View File

@ -241,7 +241,7 @@
};
&remoteproc_nsp0 {
firmware-name = "qcom/sa8540p/cdsp.mbn";
firmware-name = "qcom/sa8540p/cdsp0.mbn";
status = "okay";
};

211
arch/arm64/boot/dts/qcom/sa8775p-pmics.dtsi Normal file
View File

@ -0,0 +1,211 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
#include <dt-bindings/input/input.h>
#include <dt-bindings/spmi/spmi.h>
/ {
thermal-zones {
pmm8654au_0_thermal: pm8775-0-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmm8654au_0_temp_alarm>;
trips {
trip0 {
temperature = <105000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmm8654au_1_thermal: pm8775-1-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmm8654au_1_temp_alarm>;
trips {
trip0 {
temperature = <105000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmm8654au_2_thermal: pm8775-2-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmm8654au_2_temp_alarm>;
trips {
trip0 {
temperature = <105000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
pmm8654au_3_thermal: pm8775-3-thermal {
polling-delay-passive = <100>;
polling-delay = <0>;
thermal-sensors = <&pmm8654au_3_temp_alarm>;
trips {
trip0 {
temperature = <105000>;
hysteresis = <0>;
type = "passive";
};
trip1 {
temperature = <125000>;
hysteresis = <0>;
type = "critical";
};
};
};
};
};
&spmi_bus {
pmm8654au_0: pmic@0 {
compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmm8654au_0_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x0 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmm8654au_0_pon: pon@1200 {
compatible = "qcom,pmk8350-pon";
reg = <0x1200>, <0x800>;
reg-names = "hlos", "pbs";
mode-recovery = <0x1>;
mode-bootloader = <0x2>;
pmm8654au_0_pon_pwrkey: pwrkey {
compatible = "qcom,pmk8350-pwrkey";
interrupts-extended = <&spmi_bus 0x0 0x12 0x7 IRQ_TYPE_EDGE_BOTH>;
linux,code = <KEY_POWER>;
debounce = <15625>;
};
pmm8654au_0_pon_resin: resin {
compatible = "qcom,pmk8350-resin";
interrupts-extended = <&spmi_bus 0x0 0x12 0x6 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
status = "disabled";
};
};
pmm8654au_0_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmm8654au_0_gpios 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmm8654au_1: pmic@2 {
compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
reg = <0x2 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmm8654au_1_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x2 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmm8654au_1_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmm8654au_2_gpios 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmm8654au_2: pmic@4 {
compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
reg = <0x4 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmm8654au_2_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x4 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmm8654au_2_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmm8654au_2_gpios 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
pmm8654au_3: pmic@6 {
compatible = "qcom,pmm8654au", "qcom,spmi-pmic";
reg = <0x6 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pmm8654au_3_temp_alarm: temp-alarm@a00 {
compatible = "qcom,spmi-temp-alarm";
reg = <0xa00>;
interrupts-extended = <&spmi_bus 0x6 0xa 0x0 IRQ_TYPE_EDGE_BOTH>;
#thermal-sensor-cells = <0>;
};
pmm8654au_3_gpios: gpio@8800 {
compatible = "qcom,pmm8654au-gpio", "qcom,spmi-gpio";
reg = <0x8800>;
gpio-controller;
gpio-ranges = <&pmm8654au_3_gpios 0 0 12>;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
/dts-v1/;
#include "sa8775p.dtsi"
#include "sa8775p-pmics.dtsi"
/ {
model = "Qualcomm SA8775P Ride";
compatible = "qcom,sa8775p-ride", "qcom,sa8775p";
aliases {
serial0 = &uart10;
serial1 = &uart12;
serial2 = &uart17;
i2c18 = &i2c18;
spi16 = &spi16;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&i2c18 {
clock-frequency = <400000>;
pinctrl-0 = <&qup_i2c18_default>;
pinctrl-names = "default";
status = "okay";
};
&pmm8654au_0_gpios {
gpio-line-names = "DS_EN",
"POFF_COMPLETE",
"UFS0_VER_ID",
"FAST_POFF",
"DBU1_PON_DONE",
"AOSS_SLEEP",
"CAM_DES0_EN",
"CAM_DES1_EN",
"CAM_DES2_EN",
"CAM_DES3_EN",
"UEFI",
"ANALOG_PON_OPT";
};
&pmm8654au_1_gpios {
gpio-line-names = "PMIC_C_ID0",
"PMIC_C_ID1",
"UFS1_VER_ID",
"IPA_PWR",
"",
"WLAN_DBU4_EN",
"WLAN_EN",
"BT_EN",
"USB2_PWR_EN",
"USB2_FAULT";
};
&pmm8654au_2_gpios {
gpio-line-names = "PMIC_E_ID0",
"PMIC_E_ID1",
"USB0_PWR_EN",
"USB0_FAULT",
"SENSOR_IRQ_1",
"SENSOR_IRQ_2",
"SENSOR_RST",
"SGMIIO0_RST",
"SGMIIO1_RST",
"USB1_PWR_ENABLE",
"USB1_FAULT",
"VMON_SPX8";
};
&pmm8654au_3_gpios {
gpio-line-names = "PMIC_G_ID0",
"PMIC_G_ID1",
"GNSS_RST",
"GNSS_EN",
"GNSS_BOOT_MODE";
};
&qupv3_id_1 {
status = "okay";
};
&qupv3_id_2 {
status = "okay";
};
&sleep_clk {
clock-frequency = <32764>;
};
&spi16 {
pinctrl-0 = <&qup_spi16_default>;
pinctrl-names = "default";
status = "okay";
};
&tlmm {
qup_uart10_default: qup-uart10-state {
pins = "gpio46", "gpio47";
function = "qup1_se3";
};
qup_spi16_default: qup-spi16-state {
pins = "gpio86", "gpio87", "gpio88", "gpio89";
function = "qup2_se2";
drive-strength = <6>;
bias-disable;
};
qup_i2c18_default: qup-i2c18-state {
pins = "gpio95", "gpio96";
function = "qup2_se4";
drive-strength = <2>;
bias-pull-up;
};
qup_uart12_default: qup-uart12-state {
qup_uart12_cts: qup-uart12-cts-pins {
pins = "gpio52";
function = "qup1_se5";
bias-disable;
};
qup_uart12_rts: qup-uart12-rts-pins {
pins = "gpio53";
function = "qup1_se5";
bias-pull-down;
};
qup_uart12_tx: qup-uart12-tx-pins {
pins = "gpio54";
function = "qup1_se5";
bias-pull-up;
};
qup_uart12_rx: qup-uart12-rx-pins {
pins = "gpio55";
function = "qup1_se5";
bias-pull-down;
};
};
qup_uart17_default: qup-uart17-state {
qup_uart17_cts: qup-uart17-cts-pins {
pins = "gpio91";
function = "qup2_se3";
bias-disable;
};
qup_uart17_rts: qup0-uart17-rts-pins {
pins = "gpio92";
function = "qup2_se3";
bias-pull-down;
};
qup_uart17_tx: qup0-uart17-tx-pins {
pins = "gpio93";
function = "qup2_se3";
bias-pull-up;
};
qup_uart17_rx: qup0-uart17-rx-pins {
pins = "gpio94";
function = "qup2_se3";
bias-pull-down;
};
};
};
&uart10 {
compatible = "qcom,geni-debug-uart";
pinctrl-0 = <&qup_uart10_default>;
pinctrl-names = "default";
status = "okay";
};
&uart12 {
pinctrl-0 = <&qup_uart12_default>;
pinctrl-names = "default";
status = "okay";
};
&uart17 {
pinctrl-0 = <&qup_uart17_default>;
pinctrl-names = "default";
status = "okay";
};
&xo_board_clk {
clock-frequency = <38400000>;
};

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// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*/
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sa8775p-gcc.h>
#include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
clocks {
xo_board_clk: xo-board-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
sleep_clk: sleep-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
};
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@10000 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10000>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "cache";
next-level-cache = <&L3_1>;
L3_1: l3-cache {
compatible = "cache";
};
};
};
CPU5: cpu@10100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10100>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "cache";
next-level-cache = <&L3_1>;
};
};
CPU6: cpu@10200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10200>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "cache";
next-level-cache = <&L3_1>;
};
};
CPU7: cpu@10300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10300>;
enable-method = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "cache";
next-level-cache = <&L3_1>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
};
firmware {
scm {
compatible = "qcom,scm-sa8775p", "qcom,scm";
};
};
aggre1_noc: interconnect-aggre1-noc {
compatible = "qcom,sa8775p-aggre1-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect-aggre2-noc {
compatible = "qcom,sa8775p-aggre2-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
clk_virt: interconnect-clk-virt {
compatible = "qcom,sa8775p-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
config_noc: interconnect-config-noc {
compatible = "qcom,sa8775p-config-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
dc_noc: interconnect-dc-noc {
compatible = "qcom,sa8775p-dc-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect-gem-noc {
compatible = "qcom,sa8775p-gem-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
gpdsp_anoc: interconnect-gpdsp-anoc {
compatible = "qcom,sa8775p-gpdsp-anoc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect-lpass-ag-noc {
compatible = "qcom,sa8775p-lpass-ag-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect-mc-virt {
compatible = "qcom,sa8775p-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect-mmss-noc {
compatible = "qcom,sa8775p-mmss-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
nspa_noc: interconnect-nspa-noc {
compatible = "qcom,sa8775p-nspa-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
nspb_noc: interconnect-nspb-noc {
compatible = "qcom,sa8775p-nspb-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie_anoc: interconnect-pcie-anoc {
compatible = "qcom,sa8775p-pcie-anoc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect-system-noc {
compatible = "qcom,sa8775p-system-noc";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
/* Will be updated by the bootloader. */
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x0>;
};
qup_opp_table_100mhz: opp-table-qup100mhz {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
sail_ss_mem: sail-ss@80000000 {
reg = <0x0 0x80000000 0x0 0x10000000>;
no-map;
};
hyp_mem: hyp@90000000 {
reg = <0x0 0x90000000 0x0 0x600000>;
no-map;
};
xbl_boot_mem: xbl-boot@90600000 {
reg = <0x0 0x90600000 0x0 0x200000>;
no-map;
};
aop_image_mem: aop-image@90800000 {
reg = <0x0 0x90800000 0x0 0x60000>;
no-map;
};
aop_cmd_db_mem: aop-cmd-db@90860000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x90860000 0x0 0x20000>;
no-map;
};
uefi_log: uefi-log@908b0000 {
reg = <0x0 0x908b0000 0x0 0x10000>;
no-map;
};
reserved_mem: reserved@908f0000 {
reg = <0x0 0x908f0000 0x0 0xf000>;
no-map;
};
secdata_apss_mem: secdata-apss@908ff000 {
reg = <0x0 0x908ff000 0x0 0x1000>;
no-map;
};
smem_mem: smem@90900000 {
compatible = "qcom,smem";
reg = <0x0 0x90900000 0x0 0x200000>;
no-map;
hwlocks = <&tcsr_mutex 3>;
};
cpucp_fw_mem: cpucp-fw@90b00000 {
reg = <0x0 0x90b00000 0x0 0x100000>;
no-map;
};
lpass_machine_learning_mem: lpass-machine-learning@93b00000 {
reg = <0x0 0x93b00000 0x0 0xf00000>;
no-map;
};
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@94a00000 {
reg = <0x0 0x94a00000 0x0 0x800000>;
no-map;
};
pil_camera_mem: pil-camera@95200000 {
reg = <0x0 0x95200000 0x0 0x500000>;
no-map;
};
pil_adsp_mem: pil-adsp@95c00000 {
reg = <0x0 0x95c00000 0x0 0x1e00000>;
no-map;
};
pil_gdsp0_mem: pil-gdsp0@97b00000 {
reg = <0x0 0x97b00000 0x0 0x1e00000>;
no-map;
};
pil_gdsp1_mem: pil-gdsp1@99900000 {
reg = <0x0 0x99900000 0x0 0x1e00000>;
no-map;
};
pil_cdsp0_mem: pil-cdsp0@9b800000 {
reg = <0x0 0x9b800000 0x0 0x1e00000>;
no-map;
};
pil_gpu_mem: pil-gpu@9d600000 {
reg = <0x0 0x9d600000 0x0 0x2000>;
no-map;
};
pil_cdsp1_mem: pil-cdsp1@9d700000 {
reg = <0x0 0x9d700000 0x0 0x1e00000>;
no-map;
};
pil_cvp_mem: pil-cvp@9f500000 {
reg = <0x0 0x9f500000 0x0 0x700000>;
no-map;
};
pil_video_mem: pil-video@9fc00000 {
reg = <0x0 0x9fc00000 0x0 0x700000>;
no-map;
};
hyptz_reserved_mem: hyptz-reserved@beb00000 {
reg = <0x0 0xbeb00000 0x0 0x11500000>;
no-map;
};
tz_stat_mem: tz-stat@d0000000 {
reg = <0x0 0xd0000000 0x0 0x100000>;
no-map;
};
tags_mem: tags@d0100000 {
reg = <0x0 0xd0100000 0x0 0x1200000>;
no-map;
};
qtee_mem: qtee@d1300000 {
reg = <0x0 0xd1300000 0x0 0x500000>;
no-map;
};
trusted_apps_mem: trusted-apps@d1800000 {
reg = <0x0 0xd1800000 0x0 0x3900000>;
no-map;
};
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0 0x10 0>;
gcc: clock-controller@100000 {
compatible = "qcom,sa8775p-gcc";
reg = <0x0 0x00100000 0x0 0xc7018>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>,
<0>;
power-domains = <&rpmhpd SA8775P_CX>;
};
ipcc: mailbox@408000 {
compatible = "qcom,sa8775p-ipcc", "qcom,ipcc";
reg = <0x0 0x00408000 0x0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
ranges;
clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
clock-names = "m-ahb", "s-ahb";
iommus = <&apps_smmu 0x5a3 0x0>;
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
spi16: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0x0 0x00888000 0x0 0x4000>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart17: serial@88c000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x0088c000 0x0 0x4000>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core", "qup-config";
power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
i2c18: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0x0 0x00890000 0x0 0x4000>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>,
<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core",
"qup-config",
"qup-memory";
power-domains = <&rpmhpd SA8775P_CX>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
iommus = <&apps_smmu 0x443 0x0>;
status = "disabled";
uart10: serial@a8c000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00a8c000 0x0 0x4000>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
interconnect-names = "qup-core", "qup-config";
interconnects = <&clk_virt MASTER_QUP_CORE_1 0
&clk_virt SLAVE_QUP_CORE_1 0>,
<&gem_noc MASTER_APPSS_PROC 0
&config_noc SLAVE_QUP_1 0>;
power-domains = <&rpmhpd SA8775P_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
status = "disabled";
};
uart12: serial@a94000 {
compatible = "qcom,geni-uart";
reg = <0x0 0x00a94000 0x0 0x4000>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
clock-names = "se";
interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
&clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
&config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "qup-core", "qup-config";
power-domains = <&rpmhpd SA8775P_CX>;
status = "disabled";
};
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x20000>;
#hwlock-cells = <1>;
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sa8775p-pdc", "qcom,pdc";
reg = <0x0 0x0b220000 0x0 0x30000>,
<0x0 0x17c000f0 0x0 0x64>;
qcom,pdc-ranges = <0 480 40>,
<40 140 14>,
<54 263 1>,
<55 306 4>,
<59 312 3>,
<62 374 2>,
<64 434 2>,
<66 438 2>,
<70 520 1>,
<73 523 1>,
<118 568 6>,
<124 609 3>,
<159 638 1>,
<160 720 3>,
<169 728 30>,
<199 416 2>,
<201 449 1>,
<202 89 1>,
<203 451 1>,
<204 462 1>,
<205 264 1>,
<206 579 1>,
<207 653 1>,
<208 656 1>,
<209 659 1>,
<210 122 1>,
<211 699 1>,
<212 705 1>,
<213 450 1>,
<214 643 2>,
<216 646 5>,
<221 390 5>,
<226 700 2>,
<228 440 1>,
<229 663 1>,
<230 524 2>,
<232 612 3>,
<235 723 5>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0 0x0c440000 0x0 0x1100>,
<0x0 0x0c600000 0x0 0x2000000>,
<0x0 0x0e600000 0x0 0x100000>,
<0x0 0x0e700000 0x0 0xa0000>,
<0x0 0x0c40a000 0x0 0x26000>;
reg-names = "core",
"chnls",
"obsrvr",
"intr",
"cnfg";
qcom,channel = <0>;
qcom,ee = <0>;
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
};
tlmm: pinctrl@f000000 {
compatible = "qcom,sa8775p-tlmm";
reg = <0x0 0x0f000000 0x0 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 149>;
};
apps_smmu: iommu@15000000 {
compatible = "qcom,sa8775p-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x15000000 0x0 0x100000>;
#iommu-cells = <2>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 894 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 893 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 892 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 891 IRQ_TYPE_LEVEL_HIGH>;
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
<0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
};
memtimer: timer@17c20000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17c20000 0x0 0x1000>;
ranges = <0x0 0x0 0x0 0x20000000>;
#address-cells = <1>;
#size-cells = <1>;
frame@17c21000 {
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <0>;
};
frame@17c23000 {
reg = <0x17c23000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <1>;
status = "disabled";
};
frame@17c25000 {
reg = <0x17c25000 0x1000>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <2>;
status = "disabled";
};
frame@17c27000 {
reg = <0x17c27000 0x1000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <3>;
status = "disabled";
};
frame@17c29000 {
reg = <0x17c29000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <4>;
status = "disabled";
};
frame@17c2b000 {
reg = <0x17c2b000 0x1000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <5>;
status = "disabled";
};
frame@17c2d000 {
reg = <0x17c2d000 0x1000>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
frame-number = <6>;
status = "disabled";
};
};
apps_rsc: rsc@18200000 {
compatible = "qcom,rpmh-rsc";
reg = <0x0 0x18200000 0x0 0x10000>,
<0x0 0x18210000 0x0 0x10000>,
<0x0 0x18220000 0x0 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>;
label = "apps_rsc";
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
};
rpmhcc: clock-controller {
compatible = "qcom,sa8775p-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board_clk>;
};
rpmhpd: power-controller {
compatible = "qcom,sa8775p-rpmhpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmhpd_opp_table>;
rpmhpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmhpd_opp_ret: opp-0 {
opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
};
rpmhpd_opp_min_svs: opp-1 {
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
rpmhpd_opp_low_svs: opp2 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
rpmhpd_opp_svs: opp3 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
rpmhpd_opp_svs_l1: opp-4 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
rpmhpd_opp_nom: opp-5 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
rpmhpd_opp_nom_l1: opp-6 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
rpmhpd_opp_nom_l2: opp-7 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
};
rpmhpd_opp_turbo: opp-8 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
rpmhpd_opp_turbo_l1: opp-9 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
};
};
};
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sa8775p-cpufreq-epss",
"qcom,cpufreq-epss";
reg = <0x0 0x18591000 0x0 0x1000>,
<0x0 0x18593000 0x0 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
};
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
};
};

11
arch/arm64/boot/dts/qcom/sc7180-idp.dts
View File

@ -312,14 +312,9 @@
reset-gpios = <&pm6150l_gpios 3 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
port {
panel0_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};

38
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r0.dts
View File

@ -1,38 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Kingoftown board device tree source
*
* Copyright 2021 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-kingoftown.dtsi"
/ {
model = "Google Kingoftown (rev0)";
compatible = "google,kingoftown-rev0", "qcom,sc7180";
};
/*
* In rev1+, the enable pin of pp3300_fp_tp will be tied to pp1800_l10a
* power rail instead, since kingoftown does not have FP.
*/
&pp3300_fp_tp {
gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&en_fp_rails>;
};
&tlmm {
en_fp_rails: en-fp-rails-state {
pins = "gpio74";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};

17
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown-r1.dts
View File

@ -1,17 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Kingoftown board device tree source
*
* Copyright 2021 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-parade-ps8640.dtsi"
#include "sc7180-trogdor-kingoftown.dtsi"
/ {
model = "Google Kingoftown (rev1+)";
compatible = "google,kingoftown", "qcom,sc7180";
};

10
arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dtsi → arch/arm64/boot/dts/qcom/sc7180-trogdor-kingoftown.dts
View File

@ -5,10 +5,18 @@
* Copyright 2021 Google LLC.
*/
/* This file must be included after sc7180-trogdor.dtsi */
/dts-v1/;
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-parade-ps8640.dtsi"
#include <arm/cros-ec-keyboard.dtsi>
#include "sc7180-trogdor-lte-sku.dtsi"
/ {
model = "Google Kingoftown";
compatible = "google,kingoftown", "qcom,sc7180";
};
&alc5682 {
compatible = "realtek,rt5682s";
/delete-property/ VBAT-supply;

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dts
View File

@ -26,7 +26,7 @@
interrupt-parent = <&tlmm>;
interrupts = <58 IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&pp3300_fp_tp>;
vdd-supply = <&pp3300_fp_tp>;
hid-descr-addr = <0x20>;
wakeup-source;

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r5.dts
View File

@ -23,7 +23,7 @@
/delete-node/&ap_ts;
&panel {
compatible = "innolux,n116bca-ea1", "innolux,n116bge";
compatible = "innolux,n116bca-ea1";
};
&sdhc_2 {

34
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dts
View File

@ -1,34 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Lazor board device tree source
*
* Copyright 2020 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor.dtsi"
#include "sc7180-trogdor-ti-sn65dsi86.dtsi"
#include "sc7180-trogdor-lazor.dtsi"
/ {
model = "Google Lazor (rev0)";
compatible = "google,lazor-rev0", "qcom,sc7180";
};
&sn65dsi86_out {
/*
* Lane 0 was incorrectly mapped on the cable, but we've now decided
* that the cable is canon and in -rev1+ we'll make a board change
* that means we no longer need the swizzle.
*/
lane-polarities = <1 0>;
};
&usb_hub_2_x {
vdd-supply = <&pp3300_l7c>;
};
&usb_hub_3_x {
vdd-supply = <&pp3300_l7c>;
};

22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-auo.dts
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Mrbland board device tree source
*
* Copyright 2021 Google LLC.
*
* SKU: 0x0 => 0
* - bits 7..4: Panel ID: 0x0 (AUO)
*/
/dts-v1/;
#include "sc7180-trogdor-mrbland-rev0.dtsi"
/ {
model = "Google Mrbland rev0 AUO panel board";
compatible = "google,mrbland-rev0-sku0", "qcom,sc7180";
};
&panel {
compatible = "auo,b101uan08.3";
};

22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0-boe.dts
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Mrbland board device tree source
*
* Copyright 2021 Google LLC.
*
* SKU: 0x10 => 16
* - bits 7..4: Panel ID: 0x1 (BOE)
*/
/dts-v1/;
#include "sc7180-trogdor-mrbland-rev0.dtsi"
/ {
model = "Google Mrbland rev0 BOE panel board";
compatible = "google,mrbland-rev0-sku16", "qcom,sc7180";
};
&panel {
compatible = "boe,tv101wum-n53";
};

36
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev0.dtsi
View File

@ -1,36 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Mrbland board device tree source
*
* Copyright 2021 Google LLC.
*
*/
/dts-v1/;
#include "sc7180-trogdor-mrbland.dtsi"
&avdd_lcd {
gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>;
};
&panel {
enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>;
};
&v1p8_mipi {
gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
};
/* PINCTRL - modifications to sc7180-trogdor-mrbland.dtsi */
&avdd_lcd_en {
pins = "gpio80";
};
&mipi_1800_en {
pins = "gpio81";
};
&vdd_reset_1800 {
pins = "gpio76";
};

22
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-auo.dts
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Mrbland board device tree source
*
* Copyright 2021 Google LLC.
*
* SKU: 0x600 => 1536
* - bits 11..8: Panel ID: 0x6 (AUO)
*/
/dts-v1/;
#include "sc7180-trogdor-mrbland.dtsi"
/ {
model = "Google Mrbland rev1+ AUO panel board";
compatible = "google,mrbland-sku1536", "qcom,sc7180";
};
&panel {
compatible = "auo,b101uan08.3";
};

24
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland-rev1-boe.dts
View File

@ -1,24 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Mrbland board device tree source
*
* Copyright 2021 Google LLC.
*
* SKU: 0x300 => 768
* - bits 11..8: Panel ID: 0x3 (BOE)
*/
/dts-v1/;
#include "sc7180-trogdor-mrbland.dtsi"
/ {
model = "Google Mrbland (rev1 - 2) BOE panel board";
/* Uses ID 768 on rev1 and 1024 on rev2+ */
compatible = "google,mrbland-sku1024", "google,mrbland-sku768",
"qcom,sc7180";
};
&panel {
compatible = "boe,tv101wum-n53";
};

320
arch/arm64/boot/dts/qcom/sc7180-trogdor-mrbland.dtsi
View File

@ -1,320 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Mrbland board device tree source
*
* Copyright 2021 Google LLC.
*/
/dts-v1/;
#include "sc7180-trogdor.dtsi"
/* This board only has 1 USB Type-C port. */
/delete-node/ &usb_c1;
/ {
avdd_lcd: avdd-lcd-regulator {
compatible = "regulator-fixed";
regulator-name = "avdd_lcd";
gpio = <&tlmm 88 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&avdd_lcd_en>;
vin-supply = <&pp5000_a>;
};
avee_lcd: avee-lcd-regulator {
compatible = "regulator-fixed";
regulator-name = "avee_lcd";
gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&avee_lcd_en>;
vin-supply = <&pp5000_a>;
};
v1p8_mipi: v1p8-mipi-regulator {
compatible = "regulator-fixed";
regulator-name = "v1p8_mipi";
gpio = <&tlmm 86 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&mipi_1800_en>;
vin-supply = <&pp3300_a>;
};
};
&backlight {
pwms = <&cros_ec_pwm 0>;
};
&camcc {
status = "okay";
};
&cros_ec {
keyboard-controller {
compatible = "google,cros-ec-keyb-switches";
};
};
&dsi0 {
panel: panel@0 {
/* Compatible will be filled in per-board */
reg = <0>;
enable-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&vdd_reset_1800>;
avdd-supply = <&avdd_lcd>;
avee-supply = <&avee_lcd>;
pp1800-supply = <&v1p8_mipi>;
pp3300-supply = <&pp3300_dx_edp>;
backlight = <&backlight>;
rotation = <270>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
ports {
port@1 {
endpoint {
remote-endpoint = <&panel_in>;
data-lanes = <0 1 2 3>;
};
};
};
};
&gpio_keys {
status = "okay";
};
&i2c4 {
status = "okay";
clock-frequency = <400000>;
ap_ts: touchscreen@5d {
compatible = "goodix,gt7375p";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_l>, <&ts_reset_l>;
interrupt-parent = <&tlmm>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
vdd-supply = <&pp3300_ts>;
};
};
&pp1800_uf_cam {
status = "okay";
};
&pp1800_wf_cam {
status = "okay";
};
&pp2800_uf_cam {
status = "okay";
};
&pp2800_wf_cam {
status = "okay";
};
&wifi {
qcom,ath10k-calibration-variant = "GO_MRBLAND";
};
/*
* No eDP on this board but it's logically the same signal so just give it
* a new name and assign the proper GPIO.
*/
pp3300_disp_on: &pp3300_dx_edp {
gpio = <&tlmm 85 GPIO_ACTIVE_HIGH>;
};
/* PINCTRL - modifications to sc7180-trogdor.dtsi */
/*
* No eDP on this board but it's logically the same signal so just give it
* a new name and assign the proper GPIO.
*/
tp_en: &en_pp3300_dx_edp {
pins = "gpio85";
};
/* PINCTRL - board-specific pinctrl */
&tlmm {
gpio-line-names = "HUB_RST_L",
"AP_RAM_ID0",
"AP_SKU_ID2",
"AP_RAM_ID1",
"",
"AP_RAM_ID2",
"UF_CAM_EN",
"WF_CAM_EN",
"TS_RESET_L",
"TS_INT_L",
"",
"",
"AP_EDP_BKLTEN",
"UF_CAM_MCLK",
"WF_CAM_CLK",
"",
"",
"UF_CAM_SDA",
"UF_CAM_SCL",
"WF_CAM_SDA",
"WF_CAM_SCL",
"AVEE_LCD_EN",
"",
"AMP_EN",
"",
"",
"",
"",
"HP_IRQ",
"WF_CAM_RST_L",
"UF_CAM_RST_L",
"AP_BRD_ID2",
"",
"AP_BRD_ID0",
"AP_H1_SPI_MISO",
"AP_H1_SPI_MOSI",
"AP_H1_SPI_CLK",
"AP_H1_SPI_CS_L",
"BT_UART_CTS",
"BT_UART_RTS",
"BT_UART_TXD",
"BT_UART_RXD",
"H1_AP_INT_ODL",
"",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"HP_I2C_SDA",
"HP_I2C_SCL",
"FORCED_USB_BOOT",
"AMP_BCLK",
"AMP_LRCLK",
"AMP_DIN",
"PEN_DET_ODL",
"HP_BCLK",
"HP_LRCLK",
"HP_DOUT",
"HP_DIN",
"HP_MCLK",
"AP_SKU_ID0",
"AP_EC_SPI_MISO",
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"AP_SPI_CLK",
"AP_SPI_MOSI",
"AP_SPI_MISO",
/*
* AP_FLASH_WP_L is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_L.
*/
"AP_FLASH_WP_L",
"",
"AP_SPI_CS0_L",
"",
"",
"",
"",
"WLAN_SW_CTRL",
"",
"REPORT_E",
"",
"ID0",
"",
"ID1",
"",
"",
"",
"CODEC_PWR_EN",
"HUB_EN",
"TP_EN",
"MIPI_1.8V_EN",
"VDD_RESET_1.8V",
"AVDD_LCD_EN",
"",
"AP_SKU_ID1",
"AP_RST_REQ",
"",
"AP_BRD_ID1",
"AP_EC_INT_L",
"SDM_GRFC_3",
"",
"",
"BOOT_CONFIG_4",
"BOOT_CONFIG_2",
"",
"",
"",
"",
"",
"",
"",
"BOOT_CONFIG_3",
"WCI2_LTE_COEX_TXD",
"WCI2_LTE_COEX_RXD",
"",
"",
"",
"",
"FORCED_USB_BOOT_POL",
"AP_TS_PEN_I2C_SDA",
"AP_TS_PEN_I2C_SCL",
"DP_HOT_PLUG_DET",
"EC_IN_RW_ODL";
avdd_lcd_en: avdd-lcd-en-state {
pins = "gpio88";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
avee_lcd_en: avee-lcd-en-state {
pins = "gpio21";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
mipi_1800_en: mipi-1800-en-state {
pins = "gpio86";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
vdd_reset_1800: vdd-reset-1800-state {
pins = "gpio87";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
};

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel.dtsi
View File

@ -39,7 +39,7 @@
interrupt-parent = <&tlmm>;
interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&pp3300_fp_tp>;
vdd-supply = <&pp3300_fp_tp>;
post-power-on-delay-ms = <100>;
hid-descr-addr = <0x0001>;

1
arch/arm64/boot/dts/qcom/sc7180-trogdor-pazquel360.dtsi
View File

@ -12,6 +12,7 @@
compatible = "realtek,rt5682s";
realtek,dmic1-clk-pin = <2>;
realtek,dmic-clk-rate-hz = <2048000>;
/delete-property/ VBAT-supply;
};
ap_ts_pen_1v8: &i2c4 {

11
arch/arm64/boot/dts/qcom/sc7180-trogdor-quackingstick.dtsi
View File

@ -65,14 +65,9 @@
backlight = <&backlight>;
rotation = <270>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};

22
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-boe.dts
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Wormdingler board device tree source
*
* Copyright 2021 Google LLC.
*
* SKU: 0x10 => 16
* - bits 7..4: Panel ID: 0x1 (BOE)
*/
/dts-v1/;
#include "sc7180-trogdor-wormdingler-rev0.dtsi"
/ {
model = "Google Wormdingler rev0 BOE panel board";
compatible = "google,wormdingler-rev0-sku16", "qcom,sc7180";
};
&panel {
compatible = "boe,tv110c9m-ll3";
};

22
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0-inx.dts
View File

@ -1,22 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Wormdingler board device tree source
*
* Copyright 2021 Google LLC.
*
* SKU: 0x0 => 0
* - bits 7..4: Panel ID: 0x0 (INX)
*/
/dts-v1/;
#include "sc7180-trogdor-wormdingler-rev0.dtsi"
/ {
model = "Google Wormdingler rev0 INX panel board";
compatible = "google,wormdingler-rev0-sku0", "qcom,sc7180";
};
&panel {
compatible = "innolux,hj110iz-01a";
};

36
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler-rev0.dtsi
View File

@ -1,36 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Wormdingler board device tree source
*
* Copyright 2021 Google LLC.
*
*/
/dts-v1/;
#include "sc7180-trogdor-wormdingler.dtsi"
&avdd_lcd {
gpio = <&tlmm 80 GPIO_ACTIVE_HIGH>;
};
&panel {
enable-gpios = <&tlmm 76 GPIO_ACTIVE_HIGH>;
};
&v1p8_mipi {
gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
};
/* PINCTRL - modifications to sc7180-trogdor-wormdingler.dtsi */
&avdd_lcd_en {
pins = "gpio80";
};
&mipi_1800_en {
pins = "gpio81";
};
&vdd_reset_1800 {
pins = "gpio76";
};

11
arch/arm64/boot/dts/qcom/sc7180-trogdor-wormdingler.dtsi
View File

@ -124,14 +124,9 @@
backlight = <&backlight>;
rotation = <270>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
port {
panel_in: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};

15
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -76,6 +76,7 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -103,6 +104,7 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -126,6 +128,7 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -149,6 +152,7 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -172,6 +176,7 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -195,6 +200,7 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -218,6 +224,7 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
@ -241,6 +248,7 @@
device_type = "cpu";
compatible = "qcom,kryo468";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
@ -2760,7 +2768,7 @@
system-cache-controller@9200000 {
compatible = "qcom,sc7180-llcc";
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
reg-names = "llcc0_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
@ -3019,7 +3027,6 @@
required-opps = <&rpmhpd_opp_nom>;
};
};
};
dsi0: dsi@ae94000 {
@ -3280,7 +3287,6 @@
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
cell-index = <0>;
};
sram@146aa000 {
@ -3570,7 +3576,7 @@
};
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
compatible = "qcom,sc7180-cpufreq-hw", "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
@ -3578,6 +3584,7 @@
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
#clock-cells = <1>;
};
wifi: wifi@18800000 {

2
arch/arm64/boot/dts/qcom/sc7280-crd-r3.dts
View File

@ -27,7 +27,7 @@
};
&apps_rsc {
pmg1110-regulators {
regulators-2 {
compatible = "qcom,pmg1110-rpmh-regulators";
qcom,pmic-id = "k";

2
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682-3mic.dtsi
View File

@ -94,6 +94,8 @@ hp_i2c: &i2c2 {
interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
AVDD-supply = <&pp1800_alc5682>;
DBVDD-supply = <&pp1800_alc5682>;
LDO1-IN-supply = <&pp1800_alc5682>;
MICVDD-supply = <&pp3300_codec>;
realtek,dmic1-data-pin = <1>;

2
arch/arm64/boot/dts/qcom/sc7280-herobrine-audio-rt5682.dtsi
View File

@ -76,6 +76,8 @@ hp_i2c: &i2c2 {
interrupts = <101 IRQ_TYPE_EDGE_BOTH>;
AVDD-supply = <&pp1800_alc5682>;
DBVDD-supply = <&pp1800_alc5682>;
LDO1-IN-supply = <&pp1800_alc5682>;
MICVDD-supply = <&pp3300_codec>;
realtek,dmic1-data-pin = <1>;

2
arch/arm64/boot/dts/qcom/sc7280-herobrine-crd.dts
View File

@ -40,7 +40,7 @@
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
&apps_rsc {
pmg1110-regulators {
regulators-2 {
compatible = "qcom,pmg1110-rpmh-regulators";
qcom,pmic-id = "k";

2
arch/arm64/boot/dts/qcom/sc7280-herobrine-villager.dtsi
View File

@ -33,7 +33,7 @@ ap_tp_i2c: &i2c0 {
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
hid-descr-addr = <0x20>;
vcc-supply = <&pp3300_z1>;
vdd-supply = <&pp3300_z1>;
wakeup-source;
};

2
arch/arm64/boot/dts/qcom/sc7280-idp.dts
View File

@ -25,7 +25,7 @@
};
&apps_rsc {
pmr735a-regulators {
regulators-2 {
compatible = "qcom,pmr735a-rpmh-regulators";
qcom,pmic-id = "e";

6
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View File

@ -70,7 +70,7 @@
gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>;
linux,input-type = <1>;
linux,code = <KEY_VOLUMEUP>;
gpio-key,wakeup;
wakeup-source;
debounce-interval = <15>;
linux,can-disable;
};
@ -184,7 +184,7 @@
};
&apps_rsc {
pm7325-regulators {
regulators-0 {
compatible = "qcom,pm7325-rpmh-regulators";
qcom,pmic-id = "b";
@ -279,7 +279,7 @@
};
};
pm8350c-regulators {
regulators-1 {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";

15
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
View File

@ -87,7 +87,7 @@
* are left out of here since they are managed elsewhere.
*/
pm7325-regulators {
regulators-0 {
compatible = "qcom,pm7325-rpmh-regulators";
qcom,pmic-id = "b";
@ -188,7 +188,7 @@
};
};
pm8350c-regulators {
regulators-1 {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";
@ -354,14 +354,9 @@
backlight = <&pm8350c_pwm_backlight>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_panel_in: endpoint {
remote-endpoint = <&mdss_edp_out>;
};
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss_edp_out>;
};
};
};

35
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -168,6 +168,7 @@
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -193,6 +194,7 @@
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -214,6 +216,7 @@
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -235,6 +238,7 @@
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
@ -256,6 +260,7 @@
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
@ -277,6 +282,7 @@
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
@ -298,6 +304,7 @@
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
@ -319,6 +326,7 @@
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 2>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
@ -935,7 +943,6 @@
opp-avg-kBps = <390000 0>;
};
};
};
gpi_dma0: dma-controller@900000 {
@ -2077,7 +2084,7 @@
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
@ -2131,6 +2138,8 @@
pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_n>;
dma-coherent;
iommus = <&apps_smmu 0x1c80 0x1>;
iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
@ -2677,7 +2686,8 @@
};
adreno_smmu: iommu@3da0000 {
compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500";
compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
"qcom,smmu-500", "arm,mmu-500";
reg = <0 0x03da0000 0 0x20000>;
#iommu-cells = <2>;
#global-interrupts = <2>;
@ -3289,7 +3299,6 @@
opp-avg-kBps = <200000 0>;
};
};
};
usb_1_hsphy: phy@88e3000 {
@ -3531,7 +3540,7 @@
};
pmu@90b6400 {
compatible = "qcom,sc7280-cpu-bwmon", "qcom,msm8998-bwmon";
compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0 0x090b6400 0 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
@ -3582,8 +3591,9 @@
system-cache-controller@9200000 {
compatible = "qcom,sc7280-llcc";
reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
<0 0x09600000 0 0x58000>;
reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
@ -3593,12 +3603,17 @@
<0 0x088e2000 0 0x1000>;
interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
eud_ep: endpoint {
remote-endpoint = <&usb2_role_switch>;
};
};
port@1 {
reg = <1>;
eud_con: endpoint {
remote-endpoint = <&con_eud>;
};
@ -3609,7 +3624,11 @@
eud_typec: connector {
compatible = "usb-c-connector";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
con_eud: endpoint {
remote-endpoint = <&eud_con>;
};
@ -3748,7 +3767,6 @@
required-opps = <&rpmhpd_opp_turbo>;
};
};
};
videocc: clock-controller@aaf0000 {
@ -5337,6 +5355,7 @@
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
#clock-cells = <1>;
};
};

23
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
View File

@ -413,11 +413,9 @@
backlight = <&backlight>;
ports {
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss0_dp3_out>;
};
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss0_dp3_out>;
};
};
};
@ -563,6 +561,21 @@
status = "okay";
};
&pmk8280_rtc {
nvmem-cells = <&rtc_offset>;
nvmem-cell-names = "offset";
status = "okay";
};
&pmk8280_sdam_6 {
status = "okay";
rtc_offset: rtc-offset@bc {
reg = <0xbc 0x4>;
};
};
&qup0 {
status = "okay";
};

174
arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
View File

@ -24,6 +24,7 @@
aliases {
i2c4 = &i2c4;
i2c21 = &i2c21;
serial1 = &uart2;
};
wcd938x: audio-codec {
@ -363,13 +364,18 @@
compatible = "qcom,pm8350-rpmh-regulators";
qcom,pmic-id = "b";
vdd-l1-l4-supply = <&vreg_s12b>;
vdd-l2-l7-supply = <&vreg_bob>;
vdd-l3-l5-supply = <&vreg_s11b>;
vdd-l6-l9-l10-supply = <&vreg_s12b>;
vdd-l8-supply = <&vreg_s12b>;
vreg_s10b: smps10 {
regulator-name = "vreg_s10b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_s11b: smps11 {
@ -377,6 +383,7 @@
regulator-min-microvolt = <1272000>;
regulator-max-microvolt = <1272000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_s12b: smps12 {
@ -384,6 +391,7 @@
regulator-min-microvolt = <984000>;
regulator-max-microvolt = <984000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l3b: ldo3 {
@ -413,7 +421,21 @@
regulators-1 {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";
vdd-bob-supply = <&vreg_vph_pwr>;
vdd-l1-l12-supply = <&vreg_s1c>;
vdd-l2-l8-supply = <&vreg_s1c>;
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
vdd-l6-l9-l11-supply = <&vreg_bob>;
vdd-l10-supply = <&vreg_s11b>;
vreg_s1c: smps1 {
regulator-name = "vreg_s1c";
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <1900000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l1c: ldo1 {
regulator-name = "vreg_l1c";
@ -441,6 +463,7 @@
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
regulator-always-on;
};
};
@ -449,6 +472,10 @@
qcom,pmic-id = "d";
vdd-l1-l4-supply = <&vreg_s11b>;
vdd-l2-l7-supply = <&vreg_bob>;
vdd-l3-l5-supply = <&vreg_s11b>;
vdd-l6-l9-l10-supply = <&vreg_s12b>;
vdd-l8-supply = <&vreg_s12b>;
vreg_l3d: ldo3 {
regulator-name = "vreg_l3d";
@ -527,11 +554,9 @@
backlight = <&backlight>;
power-supply = <&vreg_edp_3p3>;
ports {
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss0_dp3_out>;
};
port {
edp_panel_in: endpoint {
remote-endpoint = <&mdss0_dp3_out>;
};
};
};
@ -570,6 +595,7 @@
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 175 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_s10b>;
pinctrl-names = "default";
pinctrl-0 = <&ts0_default>;
@ -580,7 +606,7 @@
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&i2c21_default>;
pinctrl-0 = <&i2c21_default>, <&tpad_default>;
status = "okay";
@ -591,13 +617,9 @@
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&tpad_default>;
vddl-supply = <&vreg_s10b>;
wakeup-source;
status = "disabled";
};
touchpad@2c {
@ -607,9 +629,7 @@
hid-descr-addr = <0x20>;
interrupts-extended = <&tlmm 182 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
pinctrl-names = "default";
pinctrl-0 = <&tpad_default>;
vddl-supply = <&vreg_s10b>;
wakeup-source;
};
@ -621,6 +641,7 @@
hid-descr-addr = <0x1>;
interrupts-extended = <&tlmm 104 IRQ_TYPE_LEVEL_LOW>;
vdd-supply = <&vreg_misc_3p3>;
vddl-supply = <&vreg_s10b>;
pinctrl-names = "default";
pinctrl-0 = <&kybd_default>;
@ -677,6 +698,23 @@
pinctrl-0 = <&pcie4_default>;
status = "okay";
pcie@0 {
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
bus-range = <0x01 0xff>;
wifi@0 {
compatible = "pci17cb,1103";
reg = <0x10000 0x0 0x0 0x0 0x0>;
qcom,ath11k-calibration-variant = "LE_X13S";
};
};
};
&pcie4_phy {
@ -766,81 +804,109 @@
status = "okay";
};
&pmk8280_rtc {
nvmem-cells = <&rtc_offset>;
nvmem-cell-names = "offset";
status = "okay";
};
&pmk8280_sdam_6 {
status = "okay";
rtc_offset: rtc-offset@bc {
reg = <0xbc 0x4>;
};
};
&pmk8280_vadc {
status = "okay";
pmic-die-temp@3 {
reg = <PMK8350_ADC7_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "pmk8350_die_temp";
};
xo-therm@44 {
reg = <PMK8350_ADC7_AMUX_THM1_100K_PU>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "pmk8350_xo_therm";
};
pmic-die-temp@103 {
reg = <PM8350_ADC7_DIE_TEMP(1)>;
qcom,pre-scaling = <1 1>;
label = "pmc8280_1_die_temp";
};
sys-therm@144 {
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(1)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm1";
};
sys-therm@145 {
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(1)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm2";
};
sys-therm@146 {
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(1)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm3";
};
sys-therm@147 {
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(1)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm4";
};
pmic-die-temp@303 {
reg = <PM8350_ADC7_DIE_TEMP(3)>;
qcom,pre-scaling = <1 1>;
label = "pmc8280_2_die_temp";
};
sys-therm@344 {
reg = <PM8350_ADC7_AMUX_THM1_100K_PU(3)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm5";
};
sys-therm@345 {
reg = <PM8350_ADC7_AMUX_THM2_100K_PU(3)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm6";
};
sys-therm@346 {
reg = <PM8350_ADC7_AMUX_THM3_100K_PU(3)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm7";
};
sys-therm@347 {
reg = <PM8350_ADC7_AMUX_THM4_100K_PU(3)>;
qcom,hw-settle-time = <200>;
qcom,ratiometric;
label = "sys_therm8";
};
pmic-die-temp@403 {
reg = <PMR735A_ADC7_DIE_TEMP>;
qcom,pre-scaling = <1 1>;
label = "pmr735a_die_temp";
};
};
@ -884,9 +950,9 @@
"VA DMIC0", "MIC BIAS1",
"VA DMIC1", "MIC BIAS1",
"VA DMIC2", "MIC BIAS3",
"TX DMIC0", "MIC BIAS1",
"TX DMIC1", "MIC BIAS2",
"TX DMIC2", "MIC BIAS3",
"VA DMIC0", "VA MIC BIAS1",
"VA DMIC1", "VA MIC BIAS1",
"VA DMIC2", "VA MIC BIAS3",
"TX SWR_ADC1", "ADC2_OUTPUT";
wcd-playback-dai-link {
@ -937,7 +1003,7 @@
va-dai-link {
link-name = "VA Capture";
cpu {
sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>;
sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>;
};
platform {
@ -1002,6 +1068,32 @@
status = "okay";
};
&uart2 {
pinctrl-0 = <&uart2_default>;
pinctrl-names = "default";
status = "okay";
bluetooth {
compatible = "qcom,wcn6855-bt";
vddio-supply = <&vreg_s10b>;
vddbtcxmx-supply = <&vreg_s12b>;
vddrfacmn-supply = <&vreg_s12b>;
vddrfa0p8-supply = <&vreg_s12b>;
vddrfa1p2-supply = <&vreg_s11b>;
vddrfa1p7-supply = <&vreg_s1c>;
max-speed = <3200000>;
enable-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>;
swctrl-gpios = <&tlmm 132 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&bt_default>;
pinctrl-names = "default";
};
};
&usb_0 {
status = "okay";
};
@ -1062,7 +1154,7 @@
vdd-micb-supply = <&vreg_s10b>;
qcom,dmic-sample-rate = <600000>;
qcom,dmic-sample-rate = <4800000>;
status = "okay";
};
@ -1122,6 +1214,21 @@
&tlmm {
gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
bt_default: bt-default-state {
hstp-bt-en-pins {
pins = "gpio133";
function = "gpio";
drive-strength = <16>;
bias-disable;
};
hstp-sw-ctrl-pins {
pins = "gpio132";
function = "gpio";
bias-pull-down;
};
};
edp_reg_en: edp-reg-en-state {
pins = "gpio25";
function = "gpio";
@ -1132,7 +1239,6 @@
hall_int_n_default: hall-int-n-state {
pins = "gpio107";
function = "gpio";
input-enable;
bias-disable;
};
@ -1289,6 +1395,34 @@
};
};
uart2_default: uart2-default-state {
cts-pins {
pins = "gpio121";
function = "qup2";
bias-bus-hold;
};
rts-pins {
pins = "gpio122";
function = "qup2";
drive-strength = <2>;
bias-disable;
};
rx-pins {
pins = "gpio124";
function = "qup2";
bias-pull-up;
};
tx-pins {
pins = "gpio123";
function = "qup2";
drive-strength = <2>;
bias-disable;
};
};
usb0_sbu_default: usb0-sbu-state {
oe-n-pins {
pins = "gpio101";

23
arch/arm64/boot/dts/qcom/sc8280xp-pmics.dtsi
View File

@ -59,8 +59,9 @@
#size-cells = <0>;
pmk8280_pon: pon@1300 {
compatible = "qcom,pm8998-pon";
reg = <0x1300>;
compatible = "qcom,pmk8350-pon";
reg = <0x1300>, <0x800>;
reg-names = "hlos", "pbs";
pmk8280_pon_pwrkey: pwrkey {
compatible = "qcom,pmk8350-pwrkey";
@ -95,6 +96,24 @@
#thermal-sensor-cells = <1>;
status = "disabled";
};
pmk8280_rtc: rtc@6100 {
compatible = "qcom,pmk8350-rtc";
reg = <0x6100>, <0x6200>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>;
wakeup-source;
status = "disabled";
};
pmk8280_sdam_6: nvram@8500 {
compatible = "qcom,spmi-sdam";
reg = <0x8500>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x8500 0x100>;
status = "disabled";
};
};
pmc8280_1: pmic@1 {

113
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View File

@ -43,8 +43,9 @@
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a78c";
reg = <0x0 0x0>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
next-level-cache = <&L2_0>;
@ -67,8 +68,9 @@
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a78c";
reg = <0x0 0x100>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
next-level-cache = <&L2_100>;
@ -87,8 +89,9 @@
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a78c";
reg = <0x0 0x200>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
next-level-cache = <&L2_200>;
@ -107,8 +110,9 @@
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-a78c";
reg = <0x0 0x300>;
clocks = <&cpufreq_hw 0>;
enable-method = "psci";
capacity-dmips-mhz = <602>;
next-level-cache = <&L2_300>;
@ -127,8 +131,9 @@
CPU4: cpu@400 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-x1c";
reg = <0x0 0x400>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_400>;
@ -147,8 +152,9 @@
CPU5: cpu@500 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-x1c";
reg = <0x0 0x500>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_500>;
@ -167,8 +173,9 @@
CPU6: cpu@600 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-x1c";
reg = <0x0 0x600>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_600>;
@ -187,8 +194,9 @@
CPU7: cpu@700 {
device_type = "cpu";
compatible = "qcom,kryo";
compatible = "arm,cortex-x1c";
reg = <0x0 0x700>;
clocks = <&cpufreq_hw 1>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_700>;
@ -268,7 +276,6 @@
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
idle-state-name = "cluster-power-collapse";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <3263>;
exit-latency-us = <6562>;
@ -1207,6 +1214,20 @@
status = "disabled";
};
uart2: serial@988000 {
compatible = "qcom,geni-uart";
reg = <0 0x00988000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
clock-names = "se";
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
operating-points-v2 = <&qup_opp_table_100mhz>;
power-domains = <&rpmhpd SC8280XP_CX>;
interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
i2c3: i2c@98c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0098c000 0 0x4000>;
@ -1653,11 +1674,12 @@
<0x0 0x30000000 0x0 0xf1d>,
<0x0 0x30000f20 0x0 0xa8>,
<0x0 0x30001000 0x0 0x1000>,
<0x0 0x30100000 0x0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
<0x0 0x30100000 0x0 0x100000>,
<0x0 0x01c03000 0x0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>,
<0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
@ -1752,11 +1774,12 @@
<0x0 0x32000000 0x0 0xf1d>,
<0x0 0x32000f20 0x0 0xa8>,
<0x0 0x32001000 0x0 0x1000>,
<0x0 0x32100000 0x0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
<0x0 0x32100000 0x0 0x100000>,
<0x0 0x01c0b000 0x0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>,
<0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
@ -1849,11 +1872,12 @@
<0x0 0x34000000 0x0 0xf1d>,
<0x0 0x34000f20 0x0 0xa8>,
<0x0 0x34001000 0x0 0x1000>,
<0x0 0x34100000 0x0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
<0x0 0x34100000 0x0 0x100000>,
<0x0 0x01c13000 0x0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>,
<0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
@ -1949,11 +1973,12 @@
<0x0 0x38000000 0x0 0xf1d>,
<0x0 0x38000f20 0x0 0xa8>,
<0x0 0x38001000 0x0 0x1000>,
<0x0 0x38100000 0x0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
<0x0 0x38100000 0x0 0x100000>,
<0x0 0x01c1b000 0x0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>,
<0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
@ -2046,11 +2071,12 @@
<0x0 0x3c000000 0x0 0xf1d>,
<0x0 0x3c000f20 0x0 0xa8>,
<0x0 0x3c001000 0x0 0x1000>,
<0x0 0x3c100000 0x0 0x100000>;
reg-names = "parf", "dbi", "elbi", "atu", "config";
<0x0 0x3c100000 0x0 0x100000>,
<0x0 0x01c23000 0x0 0x1000>;
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>,
<0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
bus-range = <0x00 0xff>;
@ -2504,12 +2530,12 @@
qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0B 0x00 0x00>;
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0x00 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0x06 0x0f 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
#sound-dai-cells = <1>;
#address-cells = <2>;
@ -2598,9 +2624,9 @@
reg = <0 0x03330000 0 0x2000>;
interrupts-extended = <&intc GIC_SPI 959 IRQ_TYPE_LEVEL_HIGH>,
<&intc GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "core", "wake";
interrupt-names = "core", "wakeup";
clocks = <&vamacro>;
clocks = <&txmacro>;
clock-names = "iface";
label = "TX";
#sound-dai-cells = <1>;
@ -2609,15 +2635,15 @@
qcom,din-ports = <4>;
qcom,dout-ports = <0>;
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03 0x03>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x01>;
qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02 0x00>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>;
qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff 0xff>;
qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>;
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x00>;
qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00 0x01>;
status = "disabled";
};
@ -2773,7 +2799,6 @@
drive-strength = <2>;
slew-rate = <1>;
bias-bus-hold;
};
};
@ -2946,7 +2971,7 @@
};
pmu@90b6400 {
compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,msm8998-bwmon";
compatible = "qcom,sc8280xp-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0 0x090b6400 0 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
@ -2983,8 +3008,14 @@
system-cache-controller@9200000 {
compatible = "qcom,sc8280xp-llcc";
reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>;
reg-names = "llcc_base", "llcc_broadcast_base";
reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
<0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
<0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>,
<0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>,
<0 0x09600000 0 0x58000>;
reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
"llcc3_base", "llcc4_base", "llcc5_base",
"llcc6_base", "llcc7_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};
@ -3253,7 +3284,7 @@
#sound-dai-cells = <0>;
operating-points-v2 = <&mdss0_dp0_opp_table>;
power-domains = <&rpmhpd SC8280XP_CX>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
status = "disabled";
@ -3331,7 +3362,7 @@
#sound-dai-cells = <0>;
operating-points-v2 = <&mdss0_dp1_opp_table>;
power-domains = <&rpmhpd SC8280XP_CX>;
power-domains = <&rpmhpd SC8280XP_MMCX>;
status = "disabled";
@ -4040,6 +4071,7 @@
clock-names = "xo", "alternate";
#freq-domain-cells = <1>;
#clock-cells = <1>;
};
remoteproc_nsp0: remoteproc@1b300000 {
@ -4398,7 +4430,6 @@
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss1_dp1: displayport-controller@22098000 {

2
arch/arm64/boot/dts/qcom/sda660-inforce-ifc6560.dts
View File

@ -29,7 +29,7 @@
gpio-keys {
compatible = "gpio-keys";
volup {
key-volup {
label = "Volume Up";
gpios = <&pm660l_gpios 7 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;

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