Protect manipulation of c0_status against preemption and multithreading.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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8afcb5d829
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101b3531a6
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@ -33,6 +33,7 @@
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#include <asm/dsp.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/system.h>
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@ -126,10 +127,21 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data)
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__put_user (child->thread.fpu.hard.fcr31, data + 64);
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
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write_c0_status(flags);
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preempt_disable();
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if (cpu_has_mipsmt) {
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unsigned int vpflags = dvpe();
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
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write_c0_status(flags);
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evpe(vpflags);
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} else {
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp));
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write_c0_status(flags);
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}
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preempt_enable();
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__put_user (tmp, data + 65);
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} else {
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__put_user (child->thread.fpu.soft.fcr31, data + 64);
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@ -284,10 +296,21 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data)
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if (!cpu_has_fpu)
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break;
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
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write_c0_status(flags);
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preempt_disable();
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if (cpu_has_mipsmt) {
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unsigned int vpflags = dvpe();
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
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write_c0_status(flags);
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evpe(vpflags);
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} else {
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
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write_c0_status(flags);
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}
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preempt_enable();
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break;
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}
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case DSP_BASE ... DSP_BASE + 5: {
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@ -29,6 +29,7 @@
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#include <asm/dsp.h>
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#include <asm/fpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mipsmtregs.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/system.h>
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@ -191,10 +192,21 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
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if (!cpu_has_fpu)
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break;
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
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write_c0_status(flags);
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preempt_disable();
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if (cpu_has_mipsmt) {
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unsigned int vpflags = dvpe();
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
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write_c0_status(flags);
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evpe(vpflags);
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} else {
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flags = read_c0_status();
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__enable_fpu();
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__asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp));
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write_c0_status(flags);
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}
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preempt_enable();
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break;
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}
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case DSP_BASE ... DSP_BASE + 5:
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