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r8169:Correct the way of setting RTL8168DP ephy 

The original way is wrong, it always writes ephy reg 0x03.

Signed-off-by: Chunhao Lin <hau@realtek.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Chun-Hao Lin 2015-12-29 22:13:39 +08:00 committed by David S. Miller
parent c832c35f5f
commit 1016a4a1f4
1 changed files with 4 additions and 11 deletions
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15
drivers/net/ethernet/realtek/r8169.c
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@ -5818,11 +5818,10 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
void __iomem *ioaddr = tp->mmio_addr;
struct pci_dev *pdev = tp->pci_dev;
static const struct ephy_info e_info_8168d_4[] = {
{ 0x0b, ~0, 0x48 },
{ 0x19, 0x20, 0x50 },
{ 0x0c, ~0, 0x20 }
{ 0x0b, 0x0000, 0x0048 },
{ 0x19, 0x0020, 0x0050 },
{ 0x0c, 0x0100, 0x0020 }
};
int i;
rtl_csi_access_enable_1(tp);
@ -5830,13 +5829,7 @@ static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
RTL_W8(MaxTxPacketSize, TxPacketMax);
for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
const struct ephy_info *e = e_info_8168d_4 + i;
u16 w;
w = rtl_ephy_read(tp, e->offset);
rtl_ephy_write(tp, 0x03, (w & e->mask) | e->bits);
}
rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
rtl_enable_clock_request(pdev);
}