drm/nouveau/secboot: support for r367 ACR
r367 uses a different hsflcn_desc layout and LS firmware signature format, requiring a rewrite of some functions. It also makes use of the shadow region, and uses SEC as the boot falcon. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Alexandre Courbot
Ben Skeggs
parent
810997ff40
commit
0f8fb2ab1e
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@ -5,5 +5,6 @@ nvkm-y += nvkm/subdev/secboot/acr.o
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nvkm-y += nvkm/subdev/secboot/acr_r352.o
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nvkm-y += nvkm/subdev/secboot/acr_r361.o
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nvkm-y += nvkm/subdev/secboot/acr_r364.o
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nvkm-y += nvkm/subdev/secboot/acr_r367.o
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nvkm-y += nvkm/subdev/secboot/gm200.o
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nvkm-y += nvkm/subdev/secboot/gm20b.o
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@ -64,5 +64,6 @@ void *nvkm_acr_load_firmware(const struct nvkm_subdev *, const char *, size_t);
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struct nvkm_acr *acr_r352_new(unsigned long);
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struct nvkm_acr *acr_r361_new(unsigned long);
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struct nvkm_acr *acr_r364_new(unsigned long);
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struct nvkm_acr *acr_r367_new(enum nvkm_secboot_falcon, unsigned long);
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#endif
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@ -0,0 +1,388 @@
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "acr_r367.h"
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#include "acr_r361.h"
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#include <core/gpuobj.h>
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/*
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* r367 ACR: new LS signature format requires a rewrite of LS firmware and
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* blob creation functions. Also the hsflcn_desc layout has changed slightly.
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*/
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#define LSF_LSB_DEPMAP_SIZE 11
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/**
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* struct acr_r367_lsf_lsb_header - LS firmware header
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*
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* See also struct acr_r352_lsf_lsb_header for documentation.
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*/
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struct acr_r367_lsf_lsb_header {
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/**
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* LS falcon signatures
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* @prd_keys: signature to use in production mode
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* @dgb_keys: signature to use in debug mode
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* @b_prd_present: whether the production key is present
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* @b_dgb_present: whether the debug key is present
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* @falcon_id: ID of the falcon the ucode applies to
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*/
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struct {
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u8 prd_keys[2][16];
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u8 dbg_keys[2][16];
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u32 b_prd_present;
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u32 b_dbg_present;
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u32 falcon_id;
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u32 supports_versioning;
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u32 version;
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u32 depmap_count;
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u8 depmap[LSF_LSB_DEPMAP_SIZE * 2 * 4];
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u8 kdf[16];
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} signature;
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u32 ucode_off;
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u32 ucode_size;
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u32 data_size;
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u32 bl_code_size;
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u32 bl_imem_off;
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u32 bl_data_off;
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u32 bl_data_size;
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u32 app_code_off;
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u32 app_code_size;
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u32 app_data_off;
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u32 app_data_size;
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u32 flags;
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};
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/**
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* struct acr_r367_lsf_wpr_header - LS blob WPR Header
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*
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* See also struct acr_r352_lsf_wpr_header for documentation.
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*/
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struct acr_r367_lsf_wpr_header {
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u32 falcon_id;
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u32 lsb_offset;
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u32 bootstrap_owner;
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u32 lazy_bootstrap;
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u32 bin_version;
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u32 status;
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#define LSF_IMAGE_STATUS_NONE 0
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#define LSF_IMAGE_STATUS_COPY 1
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#define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED 2
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#define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED 3
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#define LSF_IMAGE_STATUS_VALIDATION_DONE 4
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#define LSF_IMAGE_STATUS_VALIDATION_SKIPPED 5
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#define LSF_IMAGE_STATUS_BOOTSTRAP_READY 6
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#define LSF_IMAGE_STATUS_REVOCATION_CHECK_FAILED 7
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};
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/**
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* struct ls_ucode_img_r367 - ucode image augmented with r367 headers
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*/
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struct ls_ucode_img_r367 {
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struct ls_ucode_img base;
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struct acr_r367_lsf_wpr_header wpr_header;
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struct acr_r367_lsf_lsb_header lsb_header;
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};
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#define ls_ucode_img_r367(i) container_of(i, struct ls_ucode_img_r367, base)
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struct ls_ucode_img *
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acr_r367_ls_ucode_img_load(const struct acr_r352 *acr,
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enum nvkm_secboot_falcon falcon_id)
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{
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const struct nvkm_subdev *subdev = acr->base.subdev;
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struct ls_ucode_img_r367 *img;
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int ret;
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img = kzalloc(sizeof(*img), GFP_KERNEL);
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if (!img)
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return ERR_PTR(-ENOMEM);
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img->base.falcon_id = falcon_id;
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ret = acr->func->ls_func[falcon_id]->load(subdev, &img->base);
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if (ret) {
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kfree(img->base.ucode_data);
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kfree(img->base.sig);
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kfree(img);
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return ERR_PTR(ret);
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}
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/* Check that the signature size matches our expectations... */
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if (img->base.sig_size != sizeof(img->lsb_header.signature)) {
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nvkm_error(subdev, "invalid signature size for %s falcon!\n",
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nvkm_secboot_falcon_name[falcon_id]);
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return ERR_PTR(-EINVAL);
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}
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/* Copy signature to the right place */
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memcpy(&img->lsb_header.signature, img->base.sig, img->base.sig_size);
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/* not needed? the signature should already have the right value */
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img->lsb_header.signature.falcon_id = falcon_id;
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return &img->base;
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}
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#define LSF_LSB_HEADER_ALIGN 256
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#define LSF_BL_DATA_ALIGN 256
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#define LSF_BL_DATA_SIZE_ALIGN 256
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#define LSF_BL_CODE_SIZE_ALIGN 256
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#define LSF_UCODE_DATA_ALIGN 4096
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static u32
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acr_r367_ls_img_fill_headers(struct acr_r352 *acr,
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struct ls_ucode_img_r367 *img, u32 offset)
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{
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struct ls_ucode_img *_img = &img->base;
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struct acr_r367_lsf_wpr_header *whdr = &img->wpr_header;
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struct acr_r367_lsf_lsb_header *lhdr = &img->lsb_header;
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struct ls_ucode_img_desc *desc = &_img->ucode_desc;
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const struct acr_r352_ls_func *func =
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acr->func->ls_func[_img->falcon_id];
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/* Fill WPR header */
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whdr->falcon_id = _img->falcon_id;
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whdr->bootstrap_owner = acr->base.boot_falcon;
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whdr->bin_version = lhdr->signature.version;
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whdr->status = LSF_IMAGE_STATUS_COPY;
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/* Skip bootstrapping falcons started by someone else than ACR */
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if (acr->lazy_bootstrap & BIT(_img->falcon_id))
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whdr->lazy_bootstrap = 1;
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/* Align, save off, and include an LSB header size */
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offset = ALIGN(offset, LSF_LSB_HEADER_ALIGN);
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whdr->lsb_offset = offset;
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offset += sizeof(*lhdr);
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/*
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* Align, save off, and include the original (static) ucode
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* image size
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*/
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offset = ALIGN(offset, LSF_UCODE_DATA_ALIGN);
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_img->ucode_off = lhdr->ucode_off = offset;
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offset += _img->ucode_size;
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/*
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* For falcons that use a boot loader (BL), we append a loader
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* desc structure on the end of the ucode image and consider
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* this the boot loader data. The host will then copy the loader
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* desc args to this space within the WPR region (before locking
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* down) and the HS bin will then copy them to DMEM 0 for the
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* loader.
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*/
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lhdr->bl_code_size = ALIGN(desc->bootloader_size,
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LSF_BL_CODE_SIZE_ALIGN);
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lhdr->ucode_size = ALIGN(desc->app_resident_data_offset,
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LSF_BL_CODE_SIZE_ALIGN) + lhdr->bl_code_size;
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lhdr->data_size = ALIGN(desc->app_size, LSF_BL_CODE_SIZE_ALIGN) +
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lhdr->bl_code_size - lhdr->ucode_size;
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/*
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* Though the BL is located at 0th offset of the image, the VA
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* is different to make sure that it doesn't collide the actual
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* OS VA range
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*/
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lhdr->bl_imem_off = desc->bootloader_imem_offset;
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lhdr->app_code_off = desc->app_start_offset +
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desc->app_resident_code_offset;
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lhdr->app_code_size = desc->app_resident_code_size;
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lhdr->app_data_off = desc->app_start_offset +
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desc->app_resident_data_offset;
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lhdr->app_data_size = desc->app_resident_data_size;
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lhdr->flags = func->lhdr_flags;
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if (_img->falcon_id == acr->base.boot_falcon)
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lhdr->flags |= LSF_FLAG_DMACTL_REQ_CTX;
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/* Align and save off BL descriptor size */
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lhdr->bl_data_size = ALIGN(func->bl_desc_size, LSF_BL_DATA_SIZE_ALIGN);
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/*
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* Align, save off, and include the additional BL data
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*/
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offset = ALIGN(offset, LSF_BL_DATA_ALIGN);
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lhdr->bl_data_off = offset;
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offset += lhdr->bl_data_size;
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return offset;
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}
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int
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acr_r367_ls_fill_headers(struct acr_r352 *acr, struct list_head *imgs)
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{
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struct ls_ucode_img_r367 *img;
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struct list_head *l;
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u32 count = 0;
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u32 offset;
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/* Count the number of images to manage */
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list_for_each(l, imgs)
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count++;
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/*
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* Start with an array of WPR headers at the base of the WPR.
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* The expectation here is that the secure falcon will do a single DMA
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* read of this array and cache it internally so it's ok to pack these.
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* Also, we add 1 to the falcon count to indicate the end of the array.
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*/
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offset = sizeof(img->wpr_header) * (count + 1);
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/*
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* Walk the managed falcons, accounting for the LSB structs
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* as well as the ucode images.
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*/
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list_for_each_entry(img, imgs, base.node) {
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offset = acr_r367_ls_img_fill_headers(acr, img, offset);
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}
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return offset;
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}
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int
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acr_r367_ls_write_wpr(struct acr_r352 *acr, struct list_head *imgs,
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struct nvkm_gpuobj *wpr_blob, u64 wpr_addr)
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{
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struct ls_ucode_img *_img;
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u32 pos = 0;
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nvkm_kmap(wpr_blob);
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list_for_each_entry(_img, imgs, node) {
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struct ls_ucode_img_r367 *img = ls_ucode_img_r367(_img);
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const struct acr_r352_ls_func *ls_func =
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acr->func->ls_func[_img->falcon_id];
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u8 gdesc[ls_func->bl_desc_size];
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nvkm_gpuobj_memcpy_to(wpr_blob, pos, &img->wpr_header,
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sizeof(img->wpr_header));
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nvkm_gpuobj_memcpy_to(wpr_blob, img->wpr_header.lsb_offset,
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&img->lsb_header, sizeof(img->lsb_header));
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/* Generate and write BL descriptor */
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memset(gdesc, 0, ls_func->bl_desc_size);
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ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc);
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nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.bl_data_off,
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gdesc, ls_func->bl_desc_size);
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/* Copy ucode */
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nvkm_gpuobj_memcpy_to(wpr_blob, img->lsb_header.ucode_off,
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_img->ucode_data, _img->ucode_size);
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pos += sizeof(img->wpr_header);
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}
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nvkm_wo32(wpr_blob, pos, NVKM_SECBOOT_FALCON_INVALID);
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nvkm_done(wpr_blob);
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return 0;
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}
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struct acr_r367_hsflcn_desc {
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u8 reserved_dmem[0x200];
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u32 signatures[4];
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u32 wpr_region_id;
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u32 wpr_offset;
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u32 mmu_memory_range;
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#define FLCN_ACR_MAX_REGIONS 2
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struct {
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u32 no_regions;
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struct {
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u32 start_addr;
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u32 end_addr;
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u32 region_id;
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u32 read_mask;
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u32 write_mask;
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u32 client_mask;
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u32 shadow_mem_start_addr;
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} region_props[FLCN_ACR_MAX_REGIONS];
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} regions;
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u32 ucode_blob_size;
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u64 ucode_blob_base __aligned(8);
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struct {
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u32 vpr_enabled;
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u32 vpr_start;
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u32 vpr_end;
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u32 hdcp_policies;
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} vpr_desc;
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};
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void
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acr_r367_fixup_hs_desc(struct acr_r352 *acr, struct nvkm_secboot *sb,
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void *_desc)
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{
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struct acr_r367_hsflcn_desc *desc = _desc;
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struct nvkm_gpuobj *ls_blob = acr->ls_blob;
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/* WPR region information if WPR is not fixed */
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if (sb->wpr_size == 0) {
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u64 wpr_start = ls_blob->addr;
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u64 wpr_end = ls_blob->addr + ls_blob->size;
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if (acr->func->shadow_blob)
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wpr_start += ls_blob->size / 2;
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desc->wpr_region_id = 1;
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desc->regions.no_regions = 2;
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desc->regions.region_props[0].start_addr = wpr_start >> 8;
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desc->regions.region_props[0].end_addr = wpr_end >> 8;
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desc->regions.region_props[0].region_id = 1;
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desc->regions.region_props[0].read_mask = 0xf;
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desc->regions.region_props[0].write_mask = 0xc;
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desc->regions.region_props[0].client_mask = 0x2;
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if (acr->func->shadow_blob)
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desc->regions.region_props[0].shadow_mem_start_addr =
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ls_blob->addr >> 8;
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else
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desc->regions.region_props[0].shadow_mem_start_addr = 0;
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} else {
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desc->ucode_blob_base = ls_blob->addr;
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desc->ucode_blob_size = ls_blob->size;
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}
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}
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const struct acr_r352_func
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acr_r367_func = {
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.fixup_hs_desc = acr_r367_fixup_hs_desc,
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.generate_hs_bl_desc = acr_r361_generate_hs_bl_desc,
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.hs_bl_desc_size = sizeof(struct acr_r361_flcn_bl_desc),
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.shadow_blob = true,
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.ls_ucode_img_load = acr_r367_ls_ucode_img_load,
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.ls_fill_headers = acr_r367_ls_fill_headers,
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.ls_write_wpr = acr_r367_ls_write_wpr,
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.ls_func = {
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[NVKM_SECBOOT_FALCON_FECS] = &acr_r361_ls_fecs_func,
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[NVKM_SECBOOT_FALCON_GPCCS] = &acr_r361_ls_gpccs_func,
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[NVKM_SECBOOT_FALCON_PMU] = &acr_r361_ls_pmu_func,
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[NVKM_SECBOOT_FALCON_SEC2] = &acr_r361_ls_sec2_func,
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},
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};
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struct nvkm_acr *
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acr_r367_new(enum nvkm_secboot_falcon boot_falcon,
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unsigned long managed_falcons)
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{
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return acr_r352_new_(&acr_r367_func, boot_falcon, managed_falcons);
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}
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@ -0,0 +1,35 @@
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
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* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NVKM_SECBOOT_ACR_R367_H__
|
||||
#define __NVKM_SECBOOT_ACR_R367_H__
|
||||
|
||||
#include "acr_r352.h"
|
||||
|
||||
void acr_r367_fixup_hs_desc(struct acr_r352 *, struct nvkm_secboot *, void *);
|
||||
|
||||
struct ls_ucode_img *acr_r367_ls_ucode_img_load(const struct acr_r352 *,
|
||||
enum nvkm_secboot_falcon);
|
||||
int acr_r367_ls_fill_headers(struct acr_r352 *, struct list_head *);
|
||||
int acr_r367_ls_write_wpr(struct acr_r352 *, struct list_head *,
|
||||
struct nvkm_gpuobj *, u64);
|
||||
#endif
|
||||
Loading…
Reference in New Issue