ARM: dts: imx7d: add fec1 and fec2 support for i.MX7d soc
Add fec1 and fec2 nodes for i.MX7d soc. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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816aa61c33
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0f629217cf
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@ -781,6 +781,42 @@
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bus-width = <4>;
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status = "disabled";
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};
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fec1: ethernet@30be0000 {
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compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
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reg = <0x30be0000 0x10000>;
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interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
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<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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status = "disabled";
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};
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fec2: ethernet@30bf0000 {
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compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec";
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reg = <0x30bf0000 0x10000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET_AXI_ROOT_CLK>,
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<&clks IMX7D_ENET2_TIME_ROOT_CLK>,
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<&clks IMX7D_PLL_ENET_MAIN_125M_CLK>,
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<&clks IMX7D_ENET_PHY_REF_ROOT_CLK>;
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clock-names = "ipg", "ahb", "ptp",
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"enet_clk_ref", "enet_out";
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fsl,num-tx-queues=<3>;
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fsl,num-rx-queues=<3>;
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status = "disabled";
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};
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};
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};
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};
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