UbiquitousOS
/
OpenCloudOS-Kernel
mirror of https://gitee.com/OpenCloudOS/OpenCloudOS-Kernel.git
11
0
Fork 0
Code Issues Projects Releases Wiki Activity

ARM: SoC fixes for 6.4, part 3 

The final bug fixes for Qualcomm and Rockchips came in, all of them
 for devicetree files:
 
  - Devices on Qualcomm SC7180/SC7280 that are cache coherent are now
    marked so correctly to fix a regression after a change in kernel behavior.
 
  - Rockchips has a few minor changes for correctness of regulator and cache
    properties, as well as fixes for incorrect behavior of the RK3568 PCI
    controller and reset pins on two boards.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEiK/NIGsWEZVxh/FrYKtH/8kJUicFAmSWBpUACgkQYKtH/8kJ
 UidebQ/+Pjt1TPVQTf8A20jC7LgyTU/oqmuC+QZbNbn/w/GDLS+mnjZe66r13q4n
 cejYVWoz4hsbDEcmW5RHetDwV1uyqnyXiZrq5zh4LkmzvGJkqCu823KYWM0h+SGg
 bzQkpXVrKVwLzg+wehpFxybq0GmIblQ44IJrGZoQpe0/mWHiT3l+icgxhD1fUUVo
 cB/qBz7tOjk3HeGec5g9tpBQX/i0IN4Q6ql4+5U3xRlDfnRIbKH4olkJD2U87cqY
 8wg+sEyNB7Qa8jcnpmtqKQFWd6J9mbUT0Qe/sQc7XW8ijfetULey8sa5kzCITA0O
 Avg9a9893Zgtx5G9E640d3q00Vo5VSb7IkgX90lNuCVI0iQzDjW44B3glOiuxfst
 srKnFjJowl9q2bG/HL+ze9QTM+Osr4bb232JX+yhko/q5B98PitxomrjHxUhMkal
 JARVRRCqNLK/gi4IsjjjseHbHvqXOiXxZiGUBTVCpCdyHTs1e0Tks2sNu8YdfPYr
 xbqU5B8Lyg+ZfEdcwz2S4bmn5XHRoGyGzomZRHsypjKpzOPXoWUtnv+BnbOor2QK
 JBqnEKnVjX3t3rBT7JEZCwHXqWYxH+CLxGkY5H2bVh2Gm/INrktANh0JhfPiPlSQ
 P/qC4Se9Ls5SF053R5Iyup2MNycejeLx3zLUjiKt8Kfcy9VVT+4=
 =lfU1
 -----END PGP SIGNATURE-----

Merge tag 'arm-fixes-6.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "The final bug fixes for Qualcomm and Rockchips came in, all of them
  for devicetree files:

   - Devices on Qualcomm SC7180/SC7280 that are cache coherent are now
     marked so correctly to fix a regression after a change in kernel
     behavior

   - Rockchips has a few minor changes for correctness of regulator and
     cache properties, as well as fixes for incorrect behavior of the
     RK3568 PCI controller and reset pins on two boards"

* tag 'arm-fixes-6.4-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  arm64: dts: qcom: sc7280: Mark SCM as dma-coherent for chrome devices
  arm64: dts: qcom: sc7180: Mark SCM as dma-coherent for trogdor
  arm64: dts: qcom: sc7180: Mark SCM as dma-coherent for IDP
  dt-bindings: firmware: qcom,scm: Document that SCM can be dma-coherent
  arm64: dts: rockchip: Fix rk356x PCIe register and range mappings
  arm64: dts: rockchip: fix button reset pin for nanopi r5c
  arm64: dts: rockchip: fix nEXTRST on SOQuartz
  arm64: dts: rockchip: add missing cache properties
  arm64: dts: rockchip: fix USB regulator on ROCK64
This commit is contained in:
Linus Torvalds 2023-06-23 16:21:59 -07:00
parent 569fa9392d ed8ff046ed
commit 0f56e65748
16 changed files with 69 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
View File

@ -71,6 +71,8 @@ properties:
minItems: 1
maxItems: 3
dma-coherent: true
interconnects:
maxItems: 1

5
arch/arm64/boot/dts/qcom/sc7180-idp.dts
View File

@ -393,6 +393,11 @@
qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
};
&scm {
/* TF-A firmware maps memory cached so mark dma-coherent to match. */
dma-coherent;
};
&sdhc_1 {
status = "okay";

5
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@ -892,6 +892,11 @@ hp_i2c: &i2c9 {
qcom,spare-regs = <&tcsr_regs_2 0xb3e4>;
};
&scm {
/* TF-A firmware maps memory cached so mark dma-coherent to match. */
dma-coherent;
};
&sdhc_1 {
status = "okay";

2
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@ -369,7 +369,7 @@
};
firmware {
scm {
scm: scm {
compatible = "qcom,scm-sc7180", "qcom,scm";
};
};

5
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi
View File

@ -79,6 +79,11 @@
firmware-name = "ath11k/WCN6750/hw1.0/wpss.mdt";
};
&scm {
/* TF-A firmware maps memory cached so mark dma-coherent to match. */
dma-coherent;
};
&wifi {
status = "okay";

2
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@ -656,7 +656,7 @@
};
firmware {
scm {
scm: scm {
compatible = "qcom,scm-sc7280", "qcom,scm";
};
};

1
arch/arm64/boot/dts/rockchip/rk3308.dtsi
View File

@ -97,6 +97,7 @@
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

14
arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
View File

@ -37,7 +37,8 @@
vin-supply = <&vcc_io>;
};
vcc_host_5v: vcc-host-5v-regulator {
/* Common enable line for all of the rails mentioned in the labels */
vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@ -48,17 +49,6 @@
vin-supply = <&vcc_sys>;
};
vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
compatible = "regulator-fixed";
gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&usb20_host_drv>;
regulator-name = "vcc_host1_5v";
regulator-always-on;
regulator-boot-on;
vin-supply = <&vcc_sys>;
};
vcc_sys: vcc-sys {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";

1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -103,6 +103,7 @@
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};

18
arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
View File

@ -28,6 +28,16 @@
regulator-max-microvolt = <5000000>;
vin-supply = <&vcc12v_dcin>;
};
vcc_sd_pwr: vcc-sd-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sd_pwr";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc3v3_sys>;
};
};
/* phy for pcie */
@ -130,13 +140,7 @@
};
&sdmmc0 {
vmmc-supply = <&sdmmc_pwr>;
status = "okay";
};
&sdmmc_pwr {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vmmc-supply = <&vcc_sd_pwr>;
status = "okay";
};

29
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
View File

@ -104,16 +104,6 @@
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc5v0_sys>;
};
sdmmc_pwr: sdmmc-pwr-regulator {
compatible = "regulator-fixed";
enable-active-high;
gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwr_h>;
regulator-name = "sdmmc_pwr";
status = "disabled";
};
};
&cpu0 {
@ -155,6 +145,19 @@
status = "disabled";
};
&gpio0 {
nextrst-hog {
gpio-hog;
/*
* GPIO_ACTIVE_LOW + output-low here means that the pin is set
* to high, because output-low decides the value pre-inversion.
*/
gpios = <RK_PA5 GPIO_ACTIVE_LOW>;
line-name = "nEXTRST";
output-low;
};
};
&gpu {
mali-supply = <&vdd_gpu>;
status = "okay";
@ -538,12 +541,6 @@
rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
sdmmc-pwr {
sdmmc_pwr_h: sdmmc-pwr-h {
rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pmu_io_domains {

2
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
View File

@ -106,7 +106,7 @@
rockchip-key {
reset_button_pin: reset-button-pin {
rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};

1
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
View File

@ -134,4 +134,3 @@
};
};
};

14
arch/arm64/boot/dts/rockchip/rk3568.dtsi
View File

@ -94,9 +94,10 @@
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0400000 0x0 0x00400000>,
<0x0 0xfe270000 0x0 0x00010000>,
<0x3 0x7f000000 0x0 0x01000000>;
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
<0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
<0x0 0xf2000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
<0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x01e00000>,
<0x03000000 0x0 0x40000000 0x3 0x40000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X1_POWERUP>;
reset-names = "pipe";
@ -146,9 +147,10 @@
power-domains = <&power RK3568_PD_PIPE>;
reg = <0x3 0xc0800000 0x0 0x00400000>,
<0x0 0xfe280000 0x0 0x00010000>,
<0x3 0xbf000000 0x0 0x01000000>;
ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
<0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
<0x0 0xf0000000 0x0 0x00100000>;
ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
<0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x01e00000>,
<0x03000000 0x0 0x40000000 0x3 0x80000000 0x0 0x40000000>;
reg-names = "dbi", "apb", "config";
resets = <&cru SRST_PCIE30X2_POWERUP>;
reset-names = "pipe";

7
arch/arm64/boot/dts/rockchip/rk356x.dtsi
View File

@ -952,7 +952,7 @@
compatible = "rockchip,rk3568-pcie";
reg = <0x3 0xc0000000 0x0 0x00400000>,
<0x0 0xfe260000 0x0 0x00010000>,
<0x3 0x3f000000 0x0 0x01000000>;
<0x0 0xf4000000 0x0 0x00100000>;
reg-names = "dbi", "apb", "config";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
@ -982,8 +982,9 @@
phys = <&combphy2 PHY_TYPE_PCIE>;
phy-names = "pcie-phy";
power-domains = <&power RK3568_PD_PIPE>;
ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
<0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x01e00000>,
<0x03000000 0x0 0x40000000 0x3 0x00000000 0x0 0x40000000>;
resets = <&cru SRST_PCIE20_POWERUP>;
reset-names = "pipe";
#address-cells = <3>;

9
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@ -229,6 +229,7 @@
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -238,6 +239,7 @@
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -247,6 +249,7 @@
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -256,6 +259,7 @@
cache-line-size = <64>;
cache-sets = <512>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -265,6 +269,7 @@
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -274,6 +279,7 @@
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -283,6 +289,7 @@
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -292,6 +299,7 @@
cache-line-size = <64>;
cache-sets = <1024>;
cache-level = <2>;
cache-unified;
next-level-cache = <&l3_cache>;
};
@ -301,6 +309,7 @@
cache-line-size = <64>;
cache-sets = <4096>;
cache-level = <3>;
cache-unified;
};
};