ARM i.MX SoC updates for v3.8
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABCAAGBQJQrjrAAAoJEPFlmONMx+ezQMMP/AkZQsc1M5qaVXsnomi7JOe3 Wz75JfZvj7LIAK+YnlCaw9KP8qYUOR/Crl3+SkraJtyY3QFlKYH/7NqEvMpa0QPX L+33AQc463D76yyv5c+Ag0V+5nTgMq070UJkqVFAnXbGfVdngkJ+sVMfwHluuPbk W/4qABMuWw0UvcCbiukZg/OdTgduUTg1ffCg8ojiXeTY9gkbxELF/cs9pa9B/Wlt oWESwqtNus9C4AnxWg9xRlKAfnyRMz6Z8ly3yr3KseBTai+/EFwdLPb8zCIw0i+J fapnEd9WhKBDPP1H+QWlgVXOIJGxIN6rzh0gKS0v3PACxu7EFQz/yvVxJVoW6qgv ZWUXQAeSnME7We1laxc4F95vxt9rdBQT31dSWldF12pq9fBF/qBxgOzfsGQEX4L/ hIYa2rXHW03wQS9u/BzWDvOnk42ty1Gy9KMtFWV2xI/GVhcH6HZDMJsMBICxTxv5 rcSX/6x2Zm7bjHPAZ6r34iHvMia51MTV2opcqGNjXPN7TOpgZfhB0d4WS0vg/4CB ayUWoO9v49N3ogis1fpKG7FOi5ukMFoljY5QCOdwLjBSxNbtDdHEbzWl1v8YbcU3 sAfRal40wMhxescidHvlC9ruyUrnT0AL1icFVgz6W/a+483O9KqD3GUhzAkvjvz5 UZwPFoSgxfFRo144L/m1 =IZiZ -----END PGP SIGNATURE----- Merge tag 'imx-soc-1' of git://git.pengutronix.de/git/imx/linux-2.6 into next/soc From Sascha Hauer: ARM i.MX SoC updates for v3.8 * tag 'imx-soc-1' of git://git.pengutronix.de/git/imx/linux-2.6: ARM i.MX6: remove gate_mask from pllv3 ARM i.MX6: Fix ethernet PLL clocks ARM i.MX6: rename PLLs according to datasheet ARM i.MX6: Add pwm support ARM i.MX51: Add pwm support ARM i.MX53: Add pwm support ARM: mx5: Replace clk_register_clkdev with clock DT lookup Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
0f327cb11f
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@ -0,0 +1,191 @@
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* Clock bindings for Freescale i.MX5
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Required properties:
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- compatible: Should be "fsl,<soc>-ccm" , where <soc> can be imx51 or imx53
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- reg: Address and length of the register set
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- interrupts: Should contain CCM interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX5
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clocks and IDs.
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Clock ID
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---------------------------
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dummy 0
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ckil 1
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osc 2
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ckih1 3
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ckih2 4
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ahb 5
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ipg 6
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axi_a 7
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axi_b 8
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uart_pred 9
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uart_root 10
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esdhc_a_pred 11
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esdhc_b_pred 12
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esdhc_c_s 13
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esdhc_d_s 14
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emi_sel 15
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emi_slow_podf 16
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nfc_podf 17
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ecspi_pred 18
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ecspi_podf 19
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usboh3_pred 20
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usboh3_podf 21
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usb_phy_pred 22
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usb_phy_podf 23
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cpu_podf 24
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di_pred 25
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tve_di 26
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tve_s 27
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uart1_ipg_gate 28
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uart1_per_gate 29
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uart2_ipg_gate 30
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uart2_per_gate 31
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uart3_ipg_gate 32
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uart3_per_gate 33
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i2c1_gate 34
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i2c2_gate 35
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gpt_ipg_gate 36
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pwm1_ipg_gate 37
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pwm1_hf_gate 38
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pwm2_ipg_gate 39
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pwm2_hf_gate 40
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gpt_hf_gate 41
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fec_gate 42
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usboh3_per_gate 43
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esdhc1_ipg_gate 44
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esdhc2_ipg_gate 45
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esdhc3_ipg_gate 46
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esdhc4_ipg_gate 47
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ssi1_ipg_gate 48
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ssi2_ipg_gate 49
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ssi3_ipg_gate 50
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ecspi1_ipg_gate 51
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ecspi1_per_gate 52
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ecspi2_ipg_gate 53
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ecspi2_per_gate 54
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cspi_ipg_gate 55
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sdma_gate 56
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emi_slow_gate 57
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ipu_s 58
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ipu_gate 59
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nfc_gate 60
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ipu_di1_gate 61
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vpu_s 62
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vpu_gate 63
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vpu_reference_gate 64
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uart4_ipg_gate 65
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uart4_per_gate 66
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uart5_ipg_gate 67
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uart5_per_gate 68
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tve_gate 69
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tve_pred 70
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esdhc1_per_gate 71
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esdhc2_per_gate 72
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esdhc3_per_gate 73
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esdhc4_per_gate 74
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usb_phy_gate 75
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hsi2c_gate 76
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mipi_hsc1_gate 77
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mipi_hsc2_gate 78
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mipi_esc_gate 79
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mipi_hsp_gate 80
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ldb_di1_div_3_5 81
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ldb_di1_div 82
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ldb_di0_div_3_5 83
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ldb_di0_div 84
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ldb_di1_gate 85
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can2_serial_gate 86
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can2_ipg_gate 87
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i2c3_gate 88
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lp_apm 89
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periph_apm 90
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main_bus 91
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ahb_max 92
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aips_tz1 93
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aips_tz2 94
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tmax1 95
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tmax2 96
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tmax3 97
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spba 98
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uart_sel 99
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esdhc_a_sel 100
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esdhc_b_sel 101
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esdhc_a_podf 102
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esdhc_b_podf 103
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ecspi_sel 104
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usboh3_sel 105
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usb_phy_sel 106
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iim_gate 107
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usboh3_gate 108
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emi_fast_gate 109
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ipu_di0_gate 110
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gpc_dvfs 111
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pll1_sw 112
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pll2_sw 113
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pll3_sw 114
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ipu_di0_sel 115
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ipu_di1_sel 116
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tve_ext_sel 117
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mx51_mipi 118
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pll4_sw 119
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ldb_di1_sel 120
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di_pll4_podf 121
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ldb_di0_sel 122
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ldb_di0_gate 123
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usb_phy1_gate 124
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usb_phy2_gate 125
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per_lp_apm 126
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per_pred1 127
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per_pred2 128
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per_podf 129
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per_root 130
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ssi_apm 131
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ssi1_root_sel 132
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ssi2_root_sel 133
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ssi3_root_sel 134
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ssi_ext1_sel 135
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ssi_ext2_sel 136
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ssi_ext1_com_sel 137
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ssi_ext2_com_sel 138
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ssi1_root_pred 139
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ssi1_root_podf 140
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ssi2_root_pred 141
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ssi2_root_podf 142
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ssi_ext1_pred 143
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ssi_ext1_podf 144
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ssi_ext2_pred 145
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ssi_ext2_podf 146
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ssi1_root_gate 147
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ssi2_root_gate 148
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ssi3_root_gate 149
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ssi_ext1_gate 150
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ssi_ext2_gate 151
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epit1_ipg_gate 152
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epit1_hf_gate 153
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epit2_ipg_gate 154
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epit2_hf_gate 155
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can_sel 156
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can1_serial_gate 157
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can1_ipg_gate 158
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Examples (for mx53):
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clks: ccm@53fd4000{
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compatible = "fsl,imx53-ccm";
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reg = <0x53fd4000 0x4000>;
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interrupts = <0 71 0x04 0 72 0x04>;
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#clock-cells = <1>;
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};
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can1: can@53fc8000 {
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compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
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reg = <0x53fc8000 0x4000>;
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interrupts = <82>;
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clocks = <&clks 158>, <&clks 157>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -187,9 +187,9 @@ clocks and IDs.
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pll3_usb_otg 172
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pll4_audio 173
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pll5_video 174
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pll6_mlb 175
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pll8_mlb 175
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pll7_usb_host 176
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pll8_enet 177
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pll6_enet 177
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ssi1_ipg 178
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ssi2_ipg 179
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ssi3_ipg 180
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@ -198,6 +198,11 @@ clocks and IDs.
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usbphy2 183
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ldb_di0_div_3_5 184
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ldb_di1_div_3_5 185
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sata_ref 186
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sata_ref_100m 187
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pcie_ref 188
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pcie_ref_125m 189
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enet_ref 190
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Examples:
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@ -87,6 +87,8 @@
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compatible = "fsl,imx51-esdhc";
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reg = <0x70004000 0x4000>;
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interrupts = <1>;
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clocks = <&clks 44>, <&clks 0>, <&clks 71>;
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clock-names = "ipg", "ahb", "per";
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status = "disabled";
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};
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@ -94,6 +96,8 @@
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compatible = "fsl,imx51-esdhc";
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reg = <0x70008000 0x4000>;
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interrupts = <2>;
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clocks = <&clks 45>, <&clks 0>, <&clks 72>;
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clock-names = "ipg", "ahb", "per";
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status = "disabled";
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};
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@ -101,6 +105,8 @@
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x7000c000 0x4000>;
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interrupts = <33>;
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clocks = <&clks 32>, <&clks 33>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -110,6 +116,8 @@
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compatible = "fsl,imx51-ecspi";
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reg = <0x70010000 0x4000>;
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interrupts = <36>;
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clocks = <&clks 51>, <&clks 52>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -117,6 +125,7 @@
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compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
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reg = <0x70014000 0x4000>;
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interrupts = <30>;
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clocks = <&clks 49>;
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fsl,fifo-depth = <15>;
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fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
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status = "disabled";
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@ -126,6 +135,8 @@
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compatible = "fsl,imx51-esdhc";
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reg = <0x70020000 0x4000>;
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interrupts = <3>;
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clocks = <&clks 46>, <&clks 0>, <&clks 73>;
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clock-names = "ipg", "ahb", "per";
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status = "disabled";
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};
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@ -133,6 +144,8 @@
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compatible = "fsl,imx51-esdhc";
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reg = <0x70024000 0x4000>;
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interrupts = <4>;
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clocks = <&clks 47>, <&clks 0>, <&clks 74>;
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clock-names = "ipg", "ahb", "per";
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status = "disabled";
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};
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};
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@ -209,12 +222,14 @@
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compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
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reg = <0x73f98000 0x4000>;
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interrupts = <58>;
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clocks = <&clks 0>;
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};
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wdog@73f9c000 { /* WDOG2 */
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compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
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reg = <0x73f9c000 0x4000>;
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interrupts = <59>;
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clocks = <&clks 0>;
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status = "disabled";
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};
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@ -394,10 +409,30 @@
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};
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};
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pwm1: pwm@73fb4000 {
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#pwm-cells = <2>;
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compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
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reg = <0x73fb4000 0x4000>;
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clocks = <&clks 37>, <&clks 38>;
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clock-names = "ipg", "per";
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interrupts = <61>;
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};
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pwm2: pwm@73fb8000 {
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#pwm-cells = <2>;
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compatible = "fsl,imx51-pwm", "fsl,imx27-pwm";
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reg = <0x73fb8000 0x4000>;
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clocks = <&clks 39>, <&clks 40>;
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clock-names = "ipg", "per";
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interrupts = <94>;
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};
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uart1: serial@73fbc000 {
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x73fbc000 0x4000>;
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interrupts = <31>;
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clocks = <&clks 28>, <&clks 29>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -405,8 +440,17 @@
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compatible = "fsl,imx51-uart", "fsl,imx21-uart";
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reg = <0x73fc0000 0x4000>;
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interrupts = <32>;
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clocks = <&clks 30>, <&clks 31>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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clks: ccm@73fd4000{
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compatible = "fsl,imx51-ccm";
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reg = <0x73fd4000 0x4000>;
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interrupts = <0 71 0x04 0 72 0x04>;
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#clock-cells = <1>;
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};
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};
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aips@80000000 { /* AIPS2 */
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@ -422,6 +466,8 @@
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compatible = "fsl,imx51-ecspi";
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reg = <0x83fac000 0x4000>;
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interrupts = <37>;
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clocks = <&clks 53>, <&clks 54>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -429,6 +475,8 @@
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compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
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reg = <0x83fb0000 0x4000>;
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interrupts = <6>;
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clocks = <&clks 56>, <&clks 56>;
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clock-names = "ipg", "ahb";
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fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin";
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};
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@ -438,6 +486,8 @@
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compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
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reg = <0x83fc0000 0x4000>;
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interrupts = <38>;
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clocks = <&clks 55>, <&clks 0>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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@ -447,6 +497,7 @@
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compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
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reg = <0x83fc4000 0x4000>;
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interrupts = <63>;
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clocks = <&clks 35>;
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status = "disabled";
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};
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@ -456,6 +507,7 @@
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compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
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reg = <0x83fc8000 0x4000>;
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interrupts = <62>;
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clocks = <&clks 34>;
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status = "disabled";
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||||
};
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@ -463,6 +515,7 @@
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compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
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reg = <0x83fcc000 0x4000>;
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interrupts = <29>;
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clocks = <&clks 48>;
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fsl,fifo-depth = <15>;
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fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
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status = "disabled";
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@ -478,6 +531,7 @@
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compatible = "fsl,imx51-nand";
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reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>;
|
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interrupts = <8>;
|
||||
clocks = <&clks 60>;
|
||||
status = "disabled";
|
||||
};
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||||
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@ -485,6 +539,7 @@
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compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
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reg = <0x83fe8000 0x4000>;
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interrupts = <96>;
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||||
clocks = <&clks 50>;
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fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
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||||
|
|
@ -494,6 +549,8 @@
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|||
compatible = "fsl,imx51-fec", "fsl,imx27-fec";
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reg = <0x83fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
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|||
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@ -92,6 +92,8 @@
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compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50004000 0x4000>;
|
||||
interrupts = <1>;
|
||||
clocks = <&clks 44>, <&clks 0>, <&clks 71>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -99,6 +101,8 @@
|
|||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50008000 0x4000>;
|
||||
interrupts = <2>;
|
||||
clocks = <&clks 45>, <&clks 0>, <&clks 72>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -106,6 +110,8 @@
|
|||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x5000c000 0x4000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clks 32>, <&clks 33>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -115,6 +121,8 @@
|
|||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x50010000 0x4000>;
|
||||
interrupts = <36>;
|
||||
clocks = <&clks 51>, <&clks 52>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -122,6 +130,7 @@
|
|||
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x50014000 0x4000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks 49>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
|
@ -131,6 +140,8 @@
|
|||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50020000 0x4000>;
|
||||
interrupts = <3>;
|
||||
clocks = <&clks 46>, <&clks 0>, <&clks 73>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -138,6 +149,8 @@
|
|||
compatible = "fsl,imx53-esdhc";
|
||||
reg = <0x50024000 0x4000>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clks 47>, <&clks 0>, <&clks 74>;
|
||||
clock-names = "ipg", "ahb", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -214,12 +227,14 @@
|
|||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f98000 0x4000>;
|
||||
interrupts = <58>;
|
||||
clocks = <&clks 0>;
|
||||
};
|
||||
|
||||
wdog@53f9c000 { /* WDOG2 */
|
||||
compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
|
||||
reg = <0x53f9c000 0x4000>;
|
||||
interrupts = <59>;
|
||||
clocks = <&clks 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -378,10 +393,30 @@
|
|||
};
|
||||
};
|
||||
|
||||
pwm1: pwm@53fb4000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x53fb4000 0x4000>;
|
||||
clocks = <&clks 37>, <&clks 38>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <61>;
|
||||
};
|
||||
|
||||
pwm2: pwm@53fb8000 {
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x53fb8000 0x4000>;
|
||||
clocks = <&clks 39>, <&clks 40>;
|
||||
clock-names = "ipg", "per";
|
||||
interrupts = <94>;
|
||||
};
|
||||
|
||||
uart1: serial@53fbc000 {
|
||||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fbc000 0x4000>;
|
||||
interrupts = <31>;
|
||||
clocks = <&clks 28>, <&clks 29>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -389,6 +424,8 @@
|
|||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53fc0000 0x4000>;
|
||||
interrupts = <32>;
|
||||
clocks = <&clks 30>, <&clks 31>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -396,6 +433,8 @@
|
|||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fc8000 0x4000>;
|
||||
interrupts = <82>;
|
||||
clocks = <&clks 158>, <&clks 157>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -403,9 +442,18 @@
|
|||
compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
|
||||
reg = <0x53fcc000 0x4000>;
|
||||
interrupts = <83>;
|
||||
clocks = <&clks 158>, <&clks 157>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clks: ccm@53fd4000{
|
||||
compatible = "fsl,imx53-ccm";
|
||||
reg = <0x53fd4000 0x4000>;
|
||||
interrupts = <0 71 0x04 0 72 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
gpio5: gpio@53fdc000 {
|
||||
compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
|
||||
reg = <0x53fdc000 0x4000>;
|
||||
|
|
@ -442,6 +490,7 @@
|
|||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x53fec000 0x4000>;
|
||||
interrupts = <64>;
|
||||
clocks = <&clks 88>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -449,6 +498,8 @@
|
|||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x53ff0000 0x4000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&clks 65>, <&clks 66>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -464,6 +515,8 @@
|
|||
compatible = "fsl,imx53-uart", "fsl,imx21-uart";
|
||||
reg = <0x63f90000 0x4000>;
|
||||
interrupts = <86>;
|
||||
clocks = <&clks 67>, <&clks 68>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -473,6 +526,8 @@
|
|||
compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
|
||||
reg = <0x63fac000 0x4000>;
|
||||
interrupts = <37>;
|
||||
clocks = <&clks 53>, <&clks 54>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -480,6 +535,8 @@
|
|||
compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
|
||||
reg = <0x63fb0000 0x4000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks 56>, <&clks 56>;
|
||||
clock-names = "ipg", "ahb";
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
|
||||
};
|
||||
|
||||
|
|
@ -489,6 +546,8 @@
|
|||
compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
|
||||
reg = <0x63fc0000 0x4000>;
|
||||
interrupts = <38>;
|
||||
clocks = <&clks 55>, <&clks 0>;
|
||||
clock-names = "ipg", "per";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -498,6 +557,7 @@
|
|||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc4000 0x4000>;
|
||||
interrupts = <63>;
|
||||
clocks = <&clks 35>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -507,6 +567,7 @@
|
|||
compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
|
||||
reg = <0x63fc8000 0x4000>;
|
||||
interrupts = <62>;
|
||||
clocks = <&clks 34>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -514,6 +575,7 @@
|
|||
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x63fcc000 0x4000>;
|
||||
interrupts = <29>;
|
||||
clocks = <&clks 48>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
|
@ -529,6 +591,7 @@
|
|||
compatible = "fsl,imx53-nand";
|
||||
reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks 60>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -536,6 +599,7 @@
|
|||
compatible = "fsl,imx53-ssi", "fsl,imx21-ssi";
|
||||
reg = <0x63fe8000 0x4000>;
|
||||
interrupts = <96>;
|
||||
clocks = <&clks 50>;
|
||||
fsl,fifo-depth = <15>;
|
||||
fsl,ssi-dma-events = <47 46 45 44>; /* TX0 RX0 TX1 RX1 */
|
||||
status = "disabled";
|
||||
|
|
@ -545,6 +609,8 @@
|
|||
compatible = "fsl,imx53-fec", "fsl,imx25-fec";
|
||||
reg = <0x63fec000 0x4000>;
|
||||
interrupts = <87>;
|
||||
clocks = <&clks 42>, <&clks 42>, <&clks 42>;
|
||||
clock-names = "ipg", "ahb", "ptp";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -268,23 +268,39 @@
|
|||
};
|
||||
|
||||
pwm@02080000 { /* PWM1 */
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02080000 0x4000>;
|
||||
interrupts = <0 83 0x04>;
|
||||
clocks = <&clks 62>, <&clks 145>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm@02084000 { /* PWM2 */
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02084000 0x4000>;
|
||||
interrupts = <0 84 0x04>;
|
||||
clocks = <&clks 62>, <&clks 146>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm@02088000 { /* PWM3 */
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02088000 0x4000>;
|
||||
interrupts = <0 85 0x04>;
|
||||
clocks = <&clks 62>, <&clks 147>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
pwm@0208c000 { /* PWM4 */
|
||||
#pwm-cells = <2>;
|
||||
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x0208c000 0x4000>;
|
||||
interrupts = <0 86 0x04>;
|
||||
clocks = <&clks 62>, <&clks 148>;
|
||||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
flexcan@02090000 { /* CAN1 */
|
||||
|
|
|
|||
|
|
@ -87,6 +87,7 @@ enum imx5_clks {
|
|||
};
|
||||
|
||||
static struct clk *clk[clk_max];
|
||||
static struct clk_onecell_data clk_data;
|
||||
|
||||
static void __init mx5_clocks_common_init(unsigned long rate_ckil,
|
||||
unsigned long rate_osc, unsigned long rate_ckih1,
|
||||
|
|
@ -318,6 +319,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
unsigned long rate_ckih1, unsigned long rate_ckih2)
|
||||
{
|
||||
int i;
|
||||
struct device_node *np;
|
||||
|
||||
clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX51_DPLL1_BASE);
|
||||
clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX51_DPLL2_BASE);
|
||||
|
|
@ -346,6 +348,11 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
pr_err("i.MX51 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx51-ccm");
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
|
||||
|
||||
clk_register_clkdev(clk[hsi2c_gate], NULL, "imx21-i2c.2");
|
||||
|
|
@ -368,10 +375,6 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
|
||||
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
|
||||
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
|
||||
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
|
||||
clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
|
||||
|
||||
/* set the usboh3 parent to pll2_sw */
|
||||
clk_set_parent(clk[usboh3_sel], clk[pll2_sw]);
|
||||
|
|
@ -395,6 +398,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
{
|
||||
int i;
|
||||
unsigned long r;
|
||||
struct device_node *np;
|
||||
|
||||
clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);
|
||||
clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);
|
||||
|
|
@ -439,6 +443,11 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
pr_err("i.MX53 clk %d: register failed with %ld\n",
|
||||
i, PTR_ERR(clk[i]));
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,imx53-ccm");
|
||||
clk_data.clks = clk;
|
||||
clk_data.clk_num = ARRAY_SIZE(clk);
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
|
||||
mx5_clocks_common_init(rate_ckil, rate_osc, rate_ckih1, rate_ckih2);
|
||||
|
||||
clk_register_clkdev(clk[vpu_gate], NULL, "imx53-vpu.0");
|
||||
|
|
@ -461,15 +470,6 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
|
|||
clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx53.3");
|
||||
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
|
||||
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
|
||||
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
|
||||
clk_register_clkdev(clk[nfc_gate], NULL, "63fdb000.nand");
|
||||
clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
|
||||
clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
|
||||
clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
|
||||
clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
|
||||
clk_register_clkdev(clk[dummy], NULL, "53fa4000.rtc");
|
||||
|
||||
/* set SDHC root clock to 200MHZ*/
|
||||
clk_set_rate(clk[esdhc_a_podf], 200000000);
|
||||
|
|
|
|||
|
|
@ -152,8 +152,9 @@ enum mx6q_clks {
|
|||
gpmi_bch_apb, gpmi_bch, gpmi_io, gpmi_apb, sata, sdma, spba, ssi1,
|
||||
ssi2, ssi3, uart_ipg, uart_serial, usboh3, usdhc1, usdhc2, usdhc3,
|
||||
usdhc4, vdo_axi, vpu_axi, cko1, pll1_sys, pll2_bus, pll3_usb_otg,
|
||||
pll4_audio, pll5_video, pll6_mlb, pll7_usb_host, pll8_enet, ssi1_ipg,
|
||||
pll4_audio, pll5_video, pll8_mlb, pll7_usb_host, pll6_enet, ssi1_ipg,
|
||||
ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5,
|
||||
sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref,
|
||||
clk_max
|
||||
};
|
||||
|
||||
|
|
@ -164,6 +165,13 @@ static enum mx6q_clks const clks_init_on[] __initconst = {
|
|||
mmdc_ch0_axi, rom,
|
||||
};
|
||||
|
||||
static struct clk_div_table clk_enet_ref_table[] = {
|
||||
{ .val = 0, .div = 20, },
|
||||
{ .val = 1, .div = 10, },
|
||||
{ .val = 2, .div = 5, },
|
||||
{ .val = 3, .div = 4, },
|
||||
};
|
||||
|
||||
int __init mx6q_clocks_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
|
|
@ -190,19 +198,29 @@ int __init mx6q_clocks_init(void)
|
|||
base = of_iomap(np, 0);
|
||||
WARN_ON(!base);
|
||||
|
||||
/* type name parent_name base gate_mask div_mask */
|
||||
clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x2000, 0x7f);
|
||||
clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x2000, 0x1);
|
||||
clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x2000, 0x3);
|
||||
clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x2000, 0x7f);
|
||||
clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x2000, 0x7f);
|
||||
clk[pll6_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll6_mlb", "osc", base + 0xd0, 0x2000, 0x0);
|
||||
clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x2000, 0x3);
|
||||
clk[pll8_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll8_enet", "osc", base + 0xe0, 0x182000, 0x3);
|
||||
/* type name parent_name base div_mask */
|
||||
clk[pll1_sys] = imx_clk_pllv3(IMX_PLLV3_SYS, "pll1_sys", "osc", base, 0x7f);
|
||||
clk[pll2_bus] = imx_clk_pllv3(IMX_PLLV3_GENERIC, "pll2_bus", "osc", base + 0x30, 0x1);
|
||||
clk[pll3_usb_otg] = imx_clk_pllv3(IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3);
|
||||
clk[pll4_audio] = imx_clk_pllv3(IMX_PLLV3_AV, "pll4_audio", "osc", base + 0x70, 0x7f);
|
||||
clk[pll5_video] = imx_clk_pllv3(IMX_PLLV3_AV, "pll5_video", "osc", base + 0xa0, 0x7f);
|
||||
clk[pll6_enet] = imx_clk_pllv3(IMX_PLLV3_ENET, "pll6_enet", "osc", base + 0xe0, 0x3);
|
||||
clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB, "pll7_usb_host","osc", base + 0x20, 0x3);
|
||||
clk[pll8_mlb] = imx_clk_pllv3(IMX_PLLV3_MLB, "pll8_mlb", "osc", base + 0xd0, 0x0);
|
||||
|
||||
clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);
|
||||
clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);
|
||||
|
||||
clk[sata_ref] = imx_clk_fixed_factor("sata_ref", "pll6_enet", 1, 5);
|
||||
clk[pcie_ref] = imx_clk_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
|
||||
|
||||
clk[sata_ref_100m] = imx_clk_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
|
||||
clk[pcie_ref_125m] = imx_clk_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
|
||||
|
||||
clk[enet_ref] = clk_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
|
||||
base + 0xe0, 0, 2, 0, clk_enet_ref_table,
|
||||
&imx_ccm_lock);
|
||||
|
||||
/* name parent_name reg idx */
|
||||
clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0);
|
||||
clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1);
|
||||
|
|
@ -358,7 +376,7 @@ int __init mx6q_clocks_init(void)
|
|||
clk[ldb_di1] = imx_clk_gate2("ldb_di1", "ldb_di1_podf", base + 0x74, 14);
|
||||
clk[ipu2_di1] = imx_clk_gate2("ipu2_di1", "ipu2_di1_sel", base + 0x74, 10);
|
||||
clk[hsi_tx] = imx_clk_gate2("hsi_tx", "hsi_tx_podf", base + 0x74, 16);
|
||||
clk[mlb] = imx_clk_gate2("mlb", "pll6_mlb", base + 0x74, 18);
|
||||
clk[mlb] = imx_clk_gate2("mlb", "pll8_mlb", base + 0x74, 18);
|
||||
clk[mmdc_ch0_axi] = imx_clk_gate2("mmdc_ch0_axi", "mmdc_ch0_axi_podf", base + 0x74, 20);
|
||||
clk[mmdc_ch1_axi] = imx_clk_gate2("mmdc_ch1_axi", "mmdc_ch1_axi_podf", base + 0x74, 22);
|
||||
clk[ocram] = imx_clk_gate2("ocram", "ahb", base + 0x74, 28);
|
||||
|
|
|
|||
|
|
@ -31,7 +31,6 @@
|
|||
* @clk_hw: clock source
|
||||
* @base: base address of PLL registers
|
||||
* @powerup_set: set POWER bit to power up the PLL
|
||||
* @gate_mask: mask of gate bits
|
||||
* @div_mask: mask of divider bits
|
||||
*
|
||||
* IMX PLL clock version 3, found on i.MX6 series. Divider for pllv3
|
||||
|
|
@ -41,7 +40,6 @@ struct clk_pllv3 {
|
|||
struct clk_hw hw;
|
||||
void __iomem *base;
|
||||
bool powerup_set;
|
||||
u32 gate_mask;
|
||||
u32 div_mask;
|
||||
};
|
||||
|
||||
|
|
@ -89,7 +87,7 @@ static int clk_pllv3_enable(struct clk_hw *hw)
|
|||
u32 val;
|
||||
|
||||
val = readl_relaxed(pll->base);
|
||||
val |= pll->gate_mask;
|
||||
val |= BM_PLL_ENABLE;
|
||||
writel_relaxed(val, pll->base);
|
||||
|
||||
return 0;
|
||||
|
|
@ -101,7 +99,7 @@ static void clk_pllv3_disable(struct clk_hw *hw)
|
|||
u32 val;
|
||||
|
||||
val = readl_relaxed(pll->base);
|
||||
val &= ~pll->gate_mask;
|
||||
val &= ~BM_PLL_ENABLE;
|
||||
writel_relaxed(val, pll->base);
|
||||
}
|
||||
|
||||
|
|
@ -287,66 +285,7 @@ static const struct clk_ops clk_pllv3_av_ops = {
|
|||
static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_pllv3 *pll = to_clk_pllv3(hw);
|
||||
u32 div = readl_relaxed(pll->base) & pll->div_mask;
|
||||
|
||||
switch (div) {
|
||||
case 0:
|
||||
return 25000000;
|
||||
case 1:
|
||||
return 50000000;
|
||||
case 2:
|
||||
return 100000000;
|
||||
case 3:
|
||||
return 125000000;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static long clk_pllv3_enet_round_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long *prate)
|
||||
{
|
||||
if (rate >= 125000000)
|
||||
rate = 125000000;
|
||||
else if (rate >= 100000000)
|
||||
rate = 100000000;
|
||||
else if (rate >= 50000000)
|
||||
rate = 50000000;
|
||||
else
|
||||
rate = 25000000;
|
||||
return rate;
|
||||
}
|
||||
|
||||
static int clk_pllv3_enet_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
struct clk_pllv3 *pll = to_clk_pllv3(hw);
|
||||
u32 val, div;
|
||||
|
||||
switch (rate) {
|
||||
case 25000000:
|
||||
div = 0;
|
||||
break;
|
||||
case 50000000:
|
||||
div = 1;
|
||||
break;
|
||||
case 100000000:
|
||||
div = 2;
|
||||
break;
|
||||
case 125000000:
|
||||
div = 3;
|
||||
break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
val = readl_relaxed(pll->base);
|
||||
val &= ~pll->div_mask;
|
||||
val |= div;
|
||||
writel_relaxed(val, pll->base);
|
||||
|
||||
return 0;
|
||||
return 500000000;
|
||||
}
|
||||
|
||||
static const struct clk_ops clk_pllv3_enet_ops = {
|
||||
|
|
@ -355,8 +294,6 @@ static const struct clk_ops clk_pllv3_enet_ops = {
|
|||
.enable = clk_pllv3_enable,
|
||||
.disable = clk_pllv3_disable,
|
||||
.recalc_rate = clk_pllv3_enet_recalc_rate,
|
||||
.round_rate = clk_pllv3_enet_round_rate,
|
||||
.set_rate = clk_pllv3_enet_set_rate,
|
||||
};
|
||||
|
||||
static const struct clk_ops clk_pllv3_mlb_ops = {
|
||||
|
|
@ -368,7 +305,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = {
|
|||
|
||||
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
|
||||
const char *parent_name, void __iomem *base,
|
||||
u32 gate_mask, u32 div_mask)
|
||||
u32 div_mask)
|
||||
{
|
||||
struct clk_pllv3 *pll;
|
||||
const struct clk_ops *ops;
|
||||
|
|
@ -400,7 +337,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
|
|||
ops = &clk_pllv3_ops;
|
||||
}
|
||||
pll->base = base;
|
||||
pll->gate_mask = gate_mask;
|
||||
pll->div_mask = div_mask;
|
||||
|
||||
init.name = name;
|
||||
|
|
|
|||
|
|
@ -22,8 +22,7 @@ enum imx_pllv3_type {
|
|||
};
|
||||
|
||||
struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,
|
||||
const char *parent_name, void __iomem *base, u32 gate_mask,
|
||||
u32 div_mask);
|
||||
const char *parent_name, void __iomem *base, u32 div_mask);
|
||||
|
||||
struct clk *clk_register_gate2(struct device *dev, const char *name,
|
||||
const char *parent_name, unsigned long flags,
|
||||
|
|
|
|||
|
|
@ -19,35 +19,9 @@
|
|||
#include "common.h"
|
||||
#include "mx51.h"
|
||||
|
||||
/*
|
||||
* Lookup table for attaching a specific name and platform_data pointer to
|
||||
* devices as they get created by of_platform_populate(). Ideally this table
|
||||
* would not exist, but the current clock implementation depends on some devices
|
||||
* having a specific name.
|
||||
*/
|
||||
static const struct of_dev_auxdata imx51_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART1_BASE_ADDR, "imx21-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART2_BASE_ADDR, "imx21-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-uart", MX51_UART3_BASE_ADDR, "imx21-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-fec", MX51_FEC_BASE_ADDR, "imx27-fec.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx51.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx51.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx51.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-esdhc", MX51_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx51.3", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-ecspi", MX51_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-cspi", MX51_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-i2c", MX51_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-sdma", MX51_SDMA_BASE_ADDR, "imx35-sdma", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx51-wdt", MX51_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx51_dt_init(void)
|
||||
{
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
imx51_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static void __init imx51_timer_init(void)
|
||||
|
|
|
|||
|
|
@ -23,34 +23,6 @@
|
|||
#include "common.h"
|
||||
#include "mx53.h"
|
||||
|
||||
/*
|
||||
* Lookup table for attaching a specific name and platform_data pointer to
|
||||
* devices as they get created by of_platform_populate(). Ideally this table
|
||||
* would not exist, but the current clock implementation depends on some devices
|
||||
* having a specific name.
|
||||
*/
|
||||
static const struct of_dev_auxdata imx53_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART1_BASE_ADDR, "imx21-uart.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART2_BASE_ADDR, "imx21-uart.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART3_BASE_ADDR, "imx21-uart.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART4_BASE_ADDR, "imx21-uart.3", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-uart", MX53_UART5_BASE_ADDR, "imx21-uart.4", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-fec", MX53_FEC_BASE_ADDR, "imx25-fec.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC1_BASE_ADDR, "sdhci-esdhc-imx53.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC2_BASE_ADDR, "sdhci-esdhc-imx53.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC3_BASE_ADDR, "sdhci-esdhc-imx53.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-esdhc", MX53_ESDHC4_BASE_ADDR, "sdhci-esdhc-imx53.3", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI1_BASE_ADDR, "imx51-ecspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-ecspi", MX53_ECSPI2_BASE_ADDR, "imx51-ecspi.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-cspi", MX53_CSPI_BASE_ADDR, "imx35-cspi.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C1_BASE_ADDR, "imx21-i2c.0", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C2_BASE_ADDR, "imx21-i2c.1", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-i2c", MX53_I2C3_BASE_ADDR, "imx21-i2c.2", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-sdma", MX53_SDMA_BASE_ADDR, "imx35-sdma", NULL),
|
||||
OF_DEV_AUXDATA("fsl,imx53-wdt", MX53_WDOG1_BASE_ADDR, "imx2-wdt.0", NULL),
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static void __init imx53_qsb_init(void)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
|
@ -69,8 +41,7 @@ static void __init imx53_dt_init(void)
|
|||
if (of_machine_is_compatible("fsl,imx53-qsb"))
|
||||
imx53_qsb_init();
|
||||
|
||||
of_platform_populate(NULL, of_default_bus_match_table,
|
||||
imx53_auxdata_lookup, NULL);
|
||||
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||
}
|
||||
|
||||
static void __init imx53_timer_init(void)
|
||||
|
|
|
|||
Loading…
Reference in New Issue