net: stmmac: xgmac: Fix XGMAC selftests
Fixup the XGMAC selftests by correctly finishing the implementation of set_filter callback. Result: $ ethtool -t enp4s0 The test result is PASS The test extra info: 1. MAC Loopback 0 2. PHY Loopback -95 3. MMC Counters -95 4. EEE -95 5. Hash Filter MC 0 6. Perfect Filter UC 0 7. MC Filter 0 8. UC Filter 0 9. Flow Control 0 Signed-off-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jose Abreu
David S. Miller
parent
0574f2ed30
commit
0efedbf11f
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@ -44,11 +44,13 @@
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#define XGMAC_CORE_INIT_RX 0
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#define XGMAC_PACKET_FILTER 0x00000008
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#define XGMAC_FILTER_RA BIT(31)
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#define XGMAC_FILTER_HPF BIT(10)
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#define XGMAC_FILTER_PCF BIT(7)
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#define XGMAC_FILTER_PM BIT(4)
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#define XGMAC_FILTER_HMC BIT(2)
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#define XGMAC_FILTER_PR BIT(0)
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#define XGMAC_HASH_TABLE(x) (0x00000010 + (x) * 4)
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#define XGMAC_MAX_HASH_TABLE 8
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#define XGMAC_RXQ_CTRL0 0x000000a0
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#define XGMAC_RXQEN(x) GENMASK((x) * 2 + 1, (x) * 2)
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#define XGMAC_RXQEN_SHIFT(x) ((x) * 2)
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@ -99,11 +101,12 @@
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#define XGMAC_MDIO_ADDR 0x00000200
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#define XGMAC_MDIO_DATA 0x00000204
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#define XGMAC_MDIO_C22P 0x00000220
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#define XGMAC_ADDR0_HIGH 0x00000300
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#define XGMAC_ADDRx_HIGH(x) (0x00000300 + (x) * 0x8)
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#define XGMAC_ADDR_MAX 32
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#define XGMAC_AE BIT(31)
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#define XGMAC_DCS GENMASK(19, 16)
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#define XGMAC_DCS_SHIFT 16
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#define XGMAC_ADDR0_LOW 0x00000304
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#define XGMAC_ADDRx_LOW(x) (0x00000304 + (x) * 0x8)
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#define XGMAC_ARP_ADDR 0x00000c10
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#define XGMAC_TIMESTAMP_STATUS 0x00000d20
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#define XGMAC_TXTSC BIT(15)
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@ -4,6 +4,8 @@
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* stmmac XGMAC support.
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*/
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#include <linux/bitrev.h>
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#include <linux/crc32.h>
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#include "stmmac.h"
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#include "dwxgmac2.h"
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@ -278,10 +280,10 @@ static void dwxgmac2_set_umac_addr(struct mac_device_info *hw,
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u32 value;
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value = (addr[5] << 8) | addr[4];
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writel(value | XGMAC_AE, ioaddr + XGMAC_ADDR0_HIGH);
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writel(value | XGMAC_AE, ioaddr + XGMAC_ADDRx_HIGH(reg_n));
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value = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
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writel(value, ioaddr + XGMAC_ADDR0_LOW);
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writel(value, ioaddr + XGMAC_ADDRx_LOW(reg_n));
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}
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static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
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@ -291,8 +293,8 @@ static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
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u32 hi_addr, lo_addr;
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/* Read the MAC address from the hardware */
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hi_addr = readl(ioaddr + XGMAC_ADDR0_HIGH);
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lo_addr = readl(ioaddr + XGMAC_ADDR0_LOW);
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hi_addr = readl(ioaddr + XGMAC_ADDRx_HIGH(reg_n));
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lo_addr = readl(ioaddr + XGMAC_ADDRx_LOW(reg_n));
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/* Extract the MAC address from the high and low words */
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addr[0] = lo_addr & 0xff;
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@ -303,19 +305,82 @@ static void dwxgmac2_get_umac_addr(struct mac_device_info *hw,
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addr[5] = (hi_addr >> 8) & 0xff;
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}
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static void dwxgmac2_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
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int mcbitslog2)
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{
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int numhashregs, regs;
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switch (mcbitslog2) {
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case 6:
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numhashregs = 2;
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break;
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case 7:
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numhashregs = 4;
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break;
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case 8:
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numhashregs = 8;
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break;
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default:
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return;
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}
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for (regs = 0; regs < numhashregs; regs++)
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writel(mcfilterbits[regs], ioaddr + XGMAC_HASH_TABLE(regs));
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}
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static void dwxgmac2_set_filter(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = (void __iomem *)dev->base_addr;
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u32 value = XGMAC_FILTER_RA;
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u32 value = readl(ioaddr + XGMAC_PACKET_FILTER);
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int mcbitslog2 = hw->mcast_bits_log2;
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u32 mc_filter[8];
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int i;
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value &= ~(XGMAC_FILTER_PR | XGMAC_FILTER_HMC | XGMAC_FILTER_PM);
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value |= XGMAC_FILTER_HPF;
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memset(mc_filter, 0, sizeof(mc_filter));
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if (dev->flags & IFF_PROMISC) {
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value |= XGMAC_FILTER_PR | XGMAC_FILTER_PCF;
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value |= XGMAC_FILTER_PR;
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value |= XGMAC_FILTER_PCF;
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} else if ((dev->flags & IFF_ALLMULTI) ||
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(netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
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(netdev_mc_count(dev) > hw->multicast_filter_bins)) {
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value |= XGMAC_FILTER_PM;
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writel(~0x0, ioaddr + XGMAC_HASH_TABLE(0));
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writel(~0x0, ioaddr + XGMAC_HASH_TABLE(1));
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for (i = 0; i < XGMAC_MAX_HASH_TABLE; i++)
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writel(~0x0, ioaddr + XGMAC_HASH_TABLE(i));
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} else if (!netdev_mc_empty(dev)) {
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struct netdev_hw_addr *ha;
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value |= XGMAC_FILTER_HMC;
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netdev_for_each_mc_addr(ha, dev) {
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int nr = (bitrev32(~crc32_le(~0, ha->addr, 6)) >>
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(32 - mcbitslog2));
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mc_filter[nr >> 5] |= (1 << (nr & 0x1F));
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}
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}
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dwxgmac2_set_mchash(ioaddr, mc_filter, mcbitslog2);
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/* Handle multiple unicast addresses */
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if (netdev_uc_count(dev) > XGMAC_ADDR_MAX) {
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value |= XGMAC_FILTER_PR;
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} else {
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struct netdev_hw_addr *ha;
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int reg = 1;
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netdev_for_each_uc_addr(ha, dev) {
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dwxgmac2_set_umac_addr(hw, ha->addr, reg);
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reg++;
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}
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for ( ; reg < XGMAC_ADDR_MAX; reg++) {
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writel(0, ioaddr + XGMAC_ADDRx_HIGH(reg));
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writel(0, ioaddr + XGMAC_ADDRx_LOW(reg));
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}
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}
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writel(value, ioaddr + XGMAC_PACKET_FILTER);
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