MIPS: Coherent Processing System SMP implementation
This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Paul Burton
Ralf Baechle
parent
b86c2247a2
commit
0ee958e102
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@ -1887,6 +1887,7 @@ config MIPS_MT_SMTC
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bool "Use all TCs on all VPEs for SMP (DEPRECATED)"
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depends on CPU_MIPS32_R2
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depends on SYS_SUPPORTS_MULTITHREADING
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depends on !MIPS_CPS
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select CPU_MIPSR2_IRQ_VI
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select CPU_MIPSR2_IRQ_EI
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select MIPS_MT
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@ -2003,6 +2004,23 @@ config MIPS_CMP
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help
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Enable Coherency Manager processor (CMP) support.
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config MIPS_CPS
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bool "MIPS Coherent Processing System support"
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depends on SYS_SUPPORTS_MIPS_CPS
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select MIPS_CM
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select MIPS_CPC
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select MIPS_GIC_IPI
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select SMP
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select SYNC_R4K if (CEVT_R4K || CSRC_R4K)
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select SYS_SUPPORTS_SMP
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select WEAK_ORDERING
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help
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Select this if you wish to run an SMP kernel across multiple cores
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within a MIPS Coherent Processing System. When this option is
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enabled the kernel will probe for other cores and boot them with
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no external assistance. It is safe to enable this when hardware
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support is unavailable.
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config MIPS_GIC_IPI
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bool
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@ -2191,6 +2209,9 @@ config SMP_UP
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config SYS_SUPPORTS_MIPS_CMP
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bool
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config SYS_SUPPORTS_MIPS_CPS
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bool
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config SYS_SUPPORTS_SMP
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bool
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@ -0,0 +1,33 @@
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __MIPS_ASM_SMP_CPS_H__
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#define __MIPS_ASM_SMP_CPS_H__
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#ifndef __ASSEMBLY__
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struct boot_config {
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unsigned int core;
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unsigned int vpe;
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unsigned long pc;
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unsigned long sp;
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unsigned long gp;
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};
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extern struct boot_config mips_cps_bootcfg;
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extern void mips_cps_core_entry(void);
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#else /* __ASSEMBLY__ */
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.extern mips_cps_bootcfg;
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#endif /* __ASSEMBLY__ */
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#endif /* __MIPS_ASM_SMP_CPS_H__ */
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@ -100,4 +100,13 @@ static inline int register_vsmp_smp_ops(void)
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#endif
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}
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#ifdef CONFIG_MIPS_CPS
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extern int register_cps_smp_ops(void);
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#else
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static inline int register_cps_smp_ops(void)
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{
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return -ENODEV;
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}
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#endif
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#endif /* __ASM_SMP_OPS_H */
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@ -53,6 +53,7 @@ obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
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obj-$(CONFIG_MIPS_MT_SMTC) += smtc.o smtc-asm.o smtc-proc.o
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obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o
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obj-$(CONFIG_MIPS_CMP) += smp-cmp.o
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obj-$(CONFIG_MIPS_CPS) += smp-cps.o cps-vec.o
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obj-$(CONFIG_MIPS_GIC_IPI) += smp-gic.o
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obj-$(CONFIG_CPU_MIPSR2) += spram.o
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@ -16,6 +16,7 @@
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#include <linux/suspend.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h>
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#include <asm/smp-cps.h>
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#include <linux/kvm_host.h>
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@ -397,3 +398,15 @@ void output_kvm_defines(void)
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OFFSET(COP0_STATUS, mips_coproc, reg[MIPS_CP0_STATUS][0]);
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BLANK();
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}
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#ifdef CONFIG_MIPS_CPS
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void output_cps_defines(void)
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{
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COMMENT(" MIPS CPS offsets. ");
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OFFSET(BOOTCFG_CORE, boot_config, core);
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OFFSET(BOOTCFG_VPE, boot_config, vpe);
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OFFSET(BOOTCFG_PC, boot_config, pc);
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OFFSET(BOOTCFG_SP, boot_config, sp);
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OFFSET(BOOTCFG_GP, boot_config, gp);
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}
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#endif
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@ -0,0 +1,191 @@
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/asmmacro.h>
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#include <asm/cacheops.h>
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#include <asm/mipsregs.h>
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#define GCR_CL_COHERENCE_OFS 0x2008
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.section .text.cps-vec
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.balign 0x1000
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.set noreorder
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LEAF(mips_cps_core_entry)
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/*
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* These first 8 bytes will be patched by cps_smp_setup to load the
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* base address of the CM GCRs into register v1.
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*/
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.quad 0
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/* Check whether we're here due to an NMI */
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mfc0 k0, CP0_STATUS
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and k0, k0, ST0_NMI
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beqz k0, not_nmi
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nop
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/* This is an NMI */
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la k0, nmi_handler
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jr k0
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nop
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not_nmi:
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/* Setup Cause */
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li t0, CAUSEF_IV
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mtc0 t0, CP0_CAUSE
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/* Setup Status */
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li t0, ST0_CU1 | ST0_CU0
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mtc0 t0, CP0_STATUS
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/*
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* Clear the bits used to index the caches. Note that the architecture
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* dictates that writing to any of TagLo or TagHi selects 0 or 2 should
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* be valid for all MIPS32 CPUs, even those for which said writes are
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* unnecessary.
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*/
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mtc0 zero, CP0_TAGLO, 0
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mtc0 zero, CP0_TAGHI, 0
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mtc0 zero, CP0_TAGLO, 2
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mtc0 zero, CP0_TAGHI, 2
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ehb
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/* Primary cache configuration is indicated by Config1 */
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mfc0 v0, CP0_CONFIG, 1
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/* Detect I-cache line size */
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_EXT t0, v0, MIPS_CONF1_IL_SHF, MIPS_CONF1_IL_SZ
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beqz t0, icache_done
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li t1, 2
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sllv t0, t1, t0
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/* Detect I-cache size */
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_EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
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xori t2, t1, 0x7
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beqz t2, 1f
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li t3, 32
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addi t1, t1, 1
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sllv t1, t3, t1
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1: /* At this point t1 == I-cache sets per way */
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_EXT t2, v0, MIPS_CONF1_IA_SHF, MIPS_CONF1_IA_SZ
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addi t2, t2, 1
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mul t1, t1, t0
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mul t1, t1, t2
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li a0, KSEG0
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add a1, a0, t1
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1: cache Index_Store_Tag_I, 0(a0)
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add a0, a0, t0
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bne a0, a1, 1b
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nop
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icache_done:
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/* Detect D-cache line size */
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_EXT t0, v0, MIPS_CONF1_DL_SHF, MIPS_CONF1_DL_SZ
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beqz t0, dcache_done
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li t1, 2
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sllv t0, t1, t0
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/* Detect D-cache size */
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_EXT t1, v0, MIPS_CONF1_DS_SHF, MIPS_CONF1_DS_SZ
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xori t2, t1, 0x7
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beqz t2, 1f
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li t3, 32
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addi t1, t1, 1
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sllv t1, t3, t1
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1: /* At this point t1 == D-cache sets per way */
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_EXT t2, v0, MIPS_CONF1_DA_SHF, MIPS_CONF1_DA_SZ
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addi t2, t2, 1
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mul t1, t1, t0
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mul t1, t1, t2
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li a0, KSEG0
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addu a1, a0, t1
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subu a1, a1, t0
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1: cache Index_Store_Tag_D, 0(a0)
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bne a0, a1, 1b
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add a0, a0, t0
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dcache_done:
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/* Set Kseg0 cacheable, coherent, write-back, write-allocate */
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mfc0 t0, CP0_CONFIG
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ori t0, 0x7
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xori t0, 0x2
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mtc0 t0, CP0_CONFIG
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ehb
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/* Enter the coherent domain */
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li t0, 0xff
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sw t0, GCR_CL_COHERENCE_OFS(v1)
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ehb
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/* Jump to kseg0 */
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la t0, 1f
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jr t0
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nop
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1: /* We're up, cached & coherent */
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/*
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* TODO: We should check the VPE number we intended to boot here, and
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* if non-zero we should start that VPE and stop this one. For
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* the moment this doesn't matter since CPUs are brought up
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* sequentially and in order, but once hotplug is implemented
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* this will need revisiting.
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*/
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/* Off we go! */
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la t0, mips_cps_bootcfg
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lw t1, BOOTCFG_PC(t0)
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lw gp, BOOTCFG_GP(t0)
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lw sp, BOOTCFG_SP(t0)
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jr t1
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nop
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END(mips_cps_core_entry)
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.org 0x200
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LEAF(excep_tlbfill)
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b .
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nop
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END(excep_tlbfill)
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.org 0x280
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LEAF(excep_xtlbfill)
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b .
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nop
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END(excep_xtlbfill)
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.org 0x300
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LEAF(excep_cache)
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b .
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nop
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END(excep_cache)
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.org 0x380
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LEAF(excep_genex)
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b .
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nop
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END(excep_genex)
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.org 0x400
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LEAF(excep_intex)
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b .
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nop
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END(excep_intex)
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.org 0x480
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LEAF(excep_ejtag)
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la k0, ejtag_debug_handler
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jr k0
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nop
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END(excep_ejtag)
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@ -398,8 +398,10 @@ static void decode_configs(struct cpuinfo_mips *c)
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mips_probe_watch_registers(c);
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#ifndef CONFIG_MIPS_CPS
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if (cpu_has_mips_r2)
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c->core = read_c0_ebase() & 0x3ff;
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#endif
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}
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#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
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@ -0,0 +1,335 @@
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/io.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <asm/cacheflush.h>
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#include <asm/gic.h>
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#include <asm/mips-cm.h>
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#include <asm/mips-cpc.h>
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#include <asm/mips_mt.h>
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#include <asm/mipsregs.h>
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#include <asm/smp-cps.h>
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#include <asm/time.h>
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#include <asm/uasm.h>
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static DECLARE_BITMAP(core_power, NR_CPUS);
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struct boot_config mips_cps_bootcfg;
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static void init_core(void)
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{
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unsigned int nvpes, t;
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u32 mvpconf0, vpeconf0, vpecontrol, tcstatus, tcbind, status;
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if (!cpu_has_mipsmt)
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return;
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/* Enter VPE configuration state */
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dvpe();
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set_c0_mvpcontrol(MVPCONTROL_VPC);
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/* Retrieve the count of VPEs in this core */
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mvpconf0 = read_c0_mvpconf0();
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nvpes = ((mvpconf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1;
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smp_num_siblings = nvpes;
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for (t = 1; t < nvpes; t++) {
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/* Use a 1:1 mapping of TC index to VPE index */
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settc(t);
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/* Bind 1 TC to this VPE */
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tcbind = read_tc_c0_tcbind();
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tcbind &= ~TCBIND_CURVPE;
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tcbind |= t << TCBIND_CURVPE_SHIFT;
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write_tc_c0_tcbind(tcbind);
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/* Set exclusive TC, non-active, master */
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vpeconf0 = read_vpe_c0_vpeconf0();
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vpeconf0 &= ~(VPECONF0_XTC | VPECONF0_VPA);
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vpeconf0 |= t << VPECONF0_XTC_SHIFT;
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vpeconf0 |= VPECONF0_MVP;
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write_vpe_c0_vpeconf0(vpeconf0);
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/* Declare TC non-active, non-allocatable & interrupt exempt */
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tcstatus = read_tc_c0_tcstatus();
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tcstatus &= ~(TCSTATUS_A | TCSTATUS_DA);
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tcstatus |= TCSTATUS_IXMT;
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write_tc_c0_tcstatus(tcstatus);
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/* Halt the TC */
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write_tc_c0_tchalt(TCHALT_H);
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/* Allow only 1 TC to execute */
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vpecontrol = read_vpe_c0_vpecontrol();
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vpecontrol &= ~VPECONTROL_TE;
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write_vpe_c0_vpecontrol(vpecontrol);
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/* Copy (most of) Status from VPE 0 */
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status = read_c0_status();
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status &= ~(ST0_IM | ST0_IE | ST0_KSU);
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status |= ST0_CU0;
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write_vpe_c0_status(status);
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/* Copy Config from VPE 0 */
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write_vpe_c0_config(read_c0_config());
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write_vpe_c0_config7(read_c0_config7());
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/* Ensure no software interrupts are pending */
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write_vpe_c0_cause(0);
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/* Sync Count */
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write_vpe_c0_count(read_c0_count());
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}
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/* Leave VPE configuration state */
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clear_c0_mvpcontrol(MVPCONTROL_VPC);
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}
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static void __init cps_smp_setup(void)
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{
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unsigned int ncores, nvpes, core_vpes;
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int c, v;
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u32 core_cfg, *entry_code;
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/* Detect & record VPE topology */
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ncores = mips_cm_numcores();
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pr_info("VPE topology ");
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for (c = nvpes = 0; c < ncores; c++) {
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if (cpu_has_mipsmt && config_enabled(CONFIG_MIPS_MT_SMP)) {
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write_gcr_cl_other(c << CM_GCR_Cx_OTHER_CORENUM_SHF);
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core_cfg = read_gcr_co_config();
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core_vpes = ((core_cfg & CM_GCR_Cx_CONFIG_PVPE_MSK) >>
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CM_GCR_Cx_CONFIG_PVPE_SHF) + 1;
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} else {
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core_vpes = 1;
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}
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pr_cont("%c%u", c ? ',' : '{', core_vpes);
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for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
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cpu_data[nvpes + v].core = c;
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#ifdef CONFIG_MIPS_MT_SMP
|
||||
cpu_data[nvpes + v].vpe_id = v;
|
||||
#endif
|
||||
}
|
||||
|
||||
nvpes += core_vpes;
|
||||
}
|
||||
pr_cont("} total %u\n", nvpes);
|
||||
|
||||
/* Indicate present CPUs (CPU being synonymous with VPE) */
|
||||
for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
|
||||
set_cpu_possible(v, true);
|
||||
set_cpu_present(v, true);
|
||||
__cpu_number_map[v] = v;
|
||||
__cpu_logical_map[v] = v;
|
||||
}
|
||||
|
||||
/* Core 0 is powered up (we're running on it) */
|
||||
bitmap_set(core_power, 0, 1);
|
||||
|
||||
/* Disable MT - we only want to run 1 TC per VPE */
|
||||
if (cpu_has_mipsmt)
|
||||
dmt();
|
||||
|
||||
/* Initialise core 0 */
|
||||
init_core();
|
||||
|
||||
/* Patch the start of mips_cps_core_entry to provide the CM base */
|
||||
entry_code = (u32 *)&mips_cps_core_entry;
|
||||
UASM_i_LA(&entry_code, 3, (long)mips_cm_base);
|
||||
|
||||
/* Make core 0 coherent with everything */
|
||||
write_gcr_cl_coherence(0xff);
|
||||
}
|
||||
|
||||
static void __init cps_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
mips_mt_set_cpuoptions();
|
||||
}
|
||||
|
||||
static void boot_core(struct boot_config *cfg)
|
||||
{
|
||||
u32 access;
|
||||
|
||||
/* Select the appropriate core */
|
||||
write_gcr_cl_other(cfg->core << CM_GCR_Cx_OTHER_CORENUM_SHF);
|
||||
|
||||
/* Set its reset vector */
|
||||
write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry));
|
||||
|
||||
/* Ensure its coherency is disabled */
|
||||
write_gcr_co_coherence(0);
|
||||
|
||||
/* Ensure the core can access the GCRs */
|
||||
access = read_gcr_access();
|
||||
access |= 1 << (CM_GCR_ACCESS_ACCESSEN_SHF + cfg->core);
|
||||
write_gcr_access(access);
|
||||
|
||||
/* Copy cfg */
|
||||
mips_cps_bootcfg = *cfg;
|
||||
|
||||
if (mips_cpc_present()) {
|
||||
/* Select the appropriate core */
|
||||
write_cpc_cl_other(cfg->core << CPC_Cx_OTHER_CORENUM_SHF);
|
||||
|
||||
/* Reset the core */
|
||||
write_cpc_co_cmd(CPC_Cx_CMD_RESET);
|
||||
} else {
|
||||
/* Take the core out of reset */
|
||||
write_gcr_co_reset_release(0);
|
||||
}
|
||||
|
||||
/* The core is now powered up */
|
||||
bitmap_set(core_power, cfg->core, 1);
|
||||
}
|
||||
|
||||
static void boot_vpe(void *info)
|
||||
{
|
||||
struct boot_config *cfg = info;
|
||||
u32 tcstatus, vpeconf0;
|
||||
|
||||
/* Enter VPE configuration state */
|
||||
dvpe();
|
||||
set_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
settc(cfg->vpe);
|
||||
|
||||
/* Set the TC restart PC */
|
||||
write_tc_c0_tcrestart((unsigned long)&smp_bootstrap);
|
||||
|
||||
/* Activate the TC, allow interrupts */
|
||||
tcstatus = read_tc_c0_tcstatus();
|
||||
tcstatus &= ~TCSTATUS_IXMT;
|
||||
tcstatus |= TCSTATUS_A;
|
||||
write_tc_c0_tcstatus(tcstatus);
|
||||
|
||||
/* Clear the TC halt bit */
|
||||
write_tc_c0_tchalt(0);
|
||||
|
||||
/* Activate the VPE */
|
||||
vpeconf0 = read_vpe_c0_vpeconf0();
|
||||
vpeconf0 |= VPECONF0_VPA;
|
||||
write_vpe_c0_vpeconf0(vpeconf0);
|
||||
|
||||
/* Set the stack & global pointer registers */
|
||||
write_tc_gpr_sp(cfg->sp);
|
||||
write_tc_gpr_gp(cfg->gp);
|
||||
|
||||
/* Leave VPE configuration state */
|
||||
clear_c0_mvpcontrol(MVPCONTROL_VPC);
|
||||
|
||||
/* Enable other VPEs to execute */
|
||||
evpe(EVPE_ENABLE);
|
||||
}
|
||||
|
||||
static void cps_boot_secondary(int cpu, struct task_struct *idle)
|
||||
{
|
||||
struct boot_config cfg;
|
||||
unsigned int remote;
|
||||
int err;
|
||||
|
||||
cfg.core = cpu_data[cpu].core;
|
||||
cfg.vpe = cpu_vpe_id(&cpu_data[cpu]);
|
||||
cfg.pc = (unsigned long)&smp_bootstrap;
|
||||
cfg.sp = __KSTK_TOS(idle);
|
||||
cfg.gp = (unsigned long)task_thread_info(idle);
|
||||
|
||||
if (!test_bit(cfg.core, core_power)) {
|
||||
/* Boot a VPE on a powered down core */
|
||||
boot_core(&cfg);
|
||||
return;
|
||||
}
|
||||
|
||||
if (cfg.core != current_cpu_data.core) {
|
||||
/* Boot a VPE on another powered up core */
|
||||
for (remote = 0; remote < NR_CPUS; remote++) {
|
||||
if (cpu_data[remote].core != cfg.core)
|
||||
continue;
|
||||
if (cpu_online(remote))
|
||||
break;
|
||||
}
|
||||
BUG_ON(remote >= NR_CPUS);
|
||||
|
||||
err = smp_call_function_single(remote, boot_vpe, &cfg, 1);
|
||||
if (err)
|
||||
panic("Failed to call remote CPU\n");
|
||||
return;
|
||||
}
|
||||
|
||||
BUG_ON(!cpu_has_mipsmt);
|
||||
|
||||
/* Boot a VPE on this core */
|
||||
boot_vpe(&cfg);
|
||||
}
|
||||
|
||||
static void cps_init_secondary(void)
|
||||
{
|
||||
/* Disable MT - we only want to run 1 TC per VPE */
|
||||
if (cpu_has_mipsmt)
|
||||
dmt();
|
||||
|
||||
/* TODO: revisit this assumption once hotplug is implemented */
|
||||
if (cpu_vpe_id(¤t_cpu_data) == 0)
|
||||
init_core();
|
||||
|
||||
change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 |
|
||||
STATUSF_IP6 | STATUSF_IP7);
|
||||
}
|
||||
|
||||
static void cps_smp_finish(void)
|
||||
{
|
||||
write_c0_compare(read_c0_count() + (8 * mips_hpt_frequency / HZ));
|
||||
|
||||
#ifdef CONFIG_MIPS_MT_FPAFF
|
||||
/* If we have an FPU, enroll ourselves in the FPU-full mask */
|
||||
if (cpu_has_fpu)
|
||||
cpu_set(smp_processor_id(), mt_fpu_cpumask);
|
||||
#endif /* CONFIG_MIPS_MT_FPAFF */
|
||||
|
||||
local_irq_enable();
|
||||
}
|
||||
|
||||
static void cps_cpus_done(void)
|
||||
{
|
||||
}
|
||||
|
||||
static struct plat_smp_ops cps_smp_ops = {
|
||||
.smp_setup = cps_smp_setup,
|
||||
.prepare_cpus = cps_prepare_cpus,
|
||||
.boot_secondary = cps_boot_secondary,
|
||||
.init_secondary = cps_init_secondary,
|
||||
.smp_finish = cps_smp_finish,
|
||||
.send_ipi_single = gic_send_ipi_single,
|
||||
.send_ipi_mask = gic_send_ipi_mask,
|
||||
.cpus_done = cps_cpus_done,
|
||||
};
|
||||
|
||||
int register_cps_smp_ops(void)
|
||||
{
|
||||
if (!mips_cm_present()) {
|
||||
pr_warn("MIPS CPS SMP unable to proceed without a CM\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* check we have a GIC - we need one for IPIs */
|
||||
if (!(read_gcr_gic_status() & CM_GCR_GIC_STATUS_EX_MSK)) {
|
||||
pr_warn("MIPS CPS SMP unable to proceed without a GIC\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
register_smp_ops(&cps_smp_ops);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -57,7 +57,7 @@ static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
|
|||
preempt_enable();
|
||||
}
|
||||
|
||||
#if defined(CONFIG_MIPS_CMP)
|
||||
#if defined(CONFIG_MIPS_CMP) || defined(CONFIG_MIPS_CPS)
|
||||
#define cpu_has_safe_index_cacheops 0
|
||||
#else
|
||||
#define cpu_has_safe_index_cacheops 1
|
||||
|
|
|
|||
Loading…
Reference in New Issue