Qualcomm Device Tree Changes for v4.14
* Fixup XO, timer nodes, and pinctrl on IPQ4019 * Add IPQ4019 RNG and wifi blocks * Update MSM8974 coresight node * Add IPQ8074 bindings -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZk7mLAAoJEFKiBbHx2RXVBIQP/iWqLPbfaad9LNyMH34dBGt5 pjWO2pQL4Q8ZAapkb9MpiyTmOXNTGAiEjbdVxR899Rr8pfZk80dtTi9ooVFBjIk+ cHlOGPSg8gnaLitDZrKc/zzkUBgVbZo5TrnF6vBl/CpT/2acPVlWxI2FLOhtRlYZ wCBT5OxqvOywyT6cs4x8nAHS2Bb+akGtcBoMI8fBVzyzn+uo1gV4c+5R2HcbqK8m Akb2cYFNV4LcgZa6KTK81FjYc9YNxyy76MeJjxbIt6A6Na0A2Hk2DWqsiMB+uUUc ijk8GnZvjQswYDI+A2gPFeXULLa4WzBJRhbYOz7m/nCM6CYtmM0gsxn65GCQbPcx 5BDOhWeuJl8o6J2EDkMFua532/5k0DGbRV34xuxg2haxF9u3XNfb24TSevTJGgPc PICgkUk8mJXwQ2MjT00LeWj9tRGcK2U8BN/pghbElAF6haUkd9Sy5F4mLn6Q8oWQ auXqaZ1h4d1x2aUf4puTP19+1Zzccl1Ay/jJJCZVqYjJlh/+wL9qniEp3gzXLhk/ +VL0rhQrYagPbcIOlJPeOBDzXsoneebYNl34YmykRL6oBhJCp/OaW1G4ESpYHc17 TmN04dBPqTZb42pEgiWM4hu9y4tJ5jTWC7T7y8rbE9bGzVHhrDcEhH7QoMhLrMmM MAK0xt6x3OPbZ51xFVFM =X0uy -----END PGP SIGNATURE----- Merge tag 'qcom-dts-for-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt Pull "Qualcomm Device Tree Changes for v4.14" from Andy Gross: * Fixup XO, timer nodes, and pinctrl on IPQ4019 * Add IPQ4019 RNG and wifi blocks * Update MSM8974 coresight node * Add IPQ8074 bindings * tag 'qcom-dts-for-4.14' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: ARM: dts: qcom: add and enable both wifi blocks on the IPQ4019 ARM: dts: qcom-msm8974: dts: Update coresight replicator ARM: dts: qcom: add pseudo random number generator on the IPQ4019 ARM: dts: ipq4019: Move xo and timer nodes to SoC dtsi ARM: dts: ipq4019: Fix pinctrl node name dt-bindings: qcom: Add IPQ8074 bindings
This commit is contained in:
Arnd Bergmann
commit
0ee72c9f25
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@ -25,6 +25,7 @@ The 'SoC' element must be one of the following strings:
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msm8994
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msm8996
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mdm9615
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ipq8074
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The 'board' element must be one of the following strings:
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@ -33,6 +34,7 @@ The 'board' element must be one of the following strings:
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dragonboard
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mtp
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sbc
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hk01
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The 'soc_version' and 'board_version' elements take the form of v<Major>.<Minor>
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where the minor number may be omitted when it's zero, i.e. v1.0 is the same
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@ -20,27 +20,12 @@
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model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
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compatible = "qcom,ipq4019";
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clocks {
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xo: xo {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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};
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soc {
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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<1 3 0xf08>,
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<1 4 0xf08>,
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<1 1 0xf08>;
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clock-frequency = <48000000>;
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rng@22000 {
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status = "ok";
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};
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pinctrl@0x01000000 {
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pinctrl@1000000 {
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serial_pins: serial_pinmux {
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mux {
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pins = "gpio60", "gpio61";
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@ -108,5 +93,13 @@
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watchdog@b017000 {
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status = "ok";
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};
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wifi@a000000 {
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status = "ok";
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};
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wifi@a800000 {
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status = "ok";
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};
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};
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};
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@ -96,6 +96,21 @@
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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xo: xo {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <1 2 0xf08>,
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<1 3 0xf08>,
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<1 4 0xf08>,
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<1 1 0xf08>;
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clock-frequency = <48000000>;
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};
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soc {
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@ -119,7 +134,15 @@
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reg = <0x1800000 0x60000>;
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};
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tlmm: pinctrl@0x01000000 {
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rng@22000 {
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compatible = "qcom,prng";
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reg = <0x22000 0x140>;
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clocks = <&gcc GCC_PRNG_AHB_CLK>;
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clock-names = "core";
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status = "disabled";
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};
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq4019-pinctrl";
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reg = <0x01000000 0x300000>;
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gpio-controller;
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@ -269,5 +292,89 @@
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compatible = "qcom,pshold";
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reg = <0x4ab000 0x4>;
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};
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wifi0: wifi@a000000 {
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compatible = "qcom,ipq4019-wifi";
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reg = <0xa000000 0x200000>;
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resets = <&gcc WIFI0_CPU_INIT_RESET>,
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<&gcc WIFI0_RADIO_SRIF_RESET>,
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<&gcc WIFI0_RADIO_WARM_RESET>,
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<&gcc WIFI0_RADIO_COLD_RESET>,
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<&gcc WIFI0_CORE_WARM_RESET>,
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<&gcc WIFI0_CORE_COLD_RESET>;
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reset-names = "wifi_cpu_init", "wifi_radio_srif",
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"wifi_radio_warm", "wifi_radio_cold",
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"wifi_core_warm", "wifi_core_cold";
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clocks = <&gcc GCC_WCSS2G_CLK>,
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<&gcc GCC_WCSS2G_REF_CLK>,
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<&gcc GCC_WCSS2G_RTC_CLK>;
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clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
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"wifi_wcss_rtc";
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interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 41 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 42 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 43 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 44 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 168 IRQ_TYPE_NONE>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7",
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"msi8", "msi9", "msi10", "msi11",
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"msi12", "msi13", "msi14", "msi15",
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"legacy";
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status = "disabled";
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};
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wifi1: wifi@a800000 {
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compatible = "qcom,ipq4019-wifi";
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reg = <0xa800000 0x200000>;
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resets = <&gcc WIFI1_CPU_INIT_RESET>,
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<&gcc WIFI1_RADIO_SRIF_RESET>,
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<&gcc WIFI1_RADIO_WARM_RESET>,
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<&gcc WIFI1_RADIO_COLD_RESET>,
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<&gcc WIFI1_CORE_WARM_RESET>,
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<&gcc WIFI1_CORE_COLD_RESET>;
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reset-names = "wifi_cpu_init", "wifi_radio_srif",
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"wifi_radio_warm", "wifi_radio_cold",
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"wifi_core_warm", "wifi_core_cold";
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clocks = <&gcc GCC_WCSS5G_CLK>,
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<&gcc GCC_WCSS5G_REF_CLK>,
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<&gcc GCC_WCSS5G_RTC_CLK>;
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clock-names = "wifi_wcss_cmd", "wifi_wcss_ref",
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"wifi_wcss_rtc";
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interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 49 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 50 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 53 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 54 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 56 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 58 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 59 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 60 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 169 IRQ_TYPE_NONE>;
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interrupt-names = "msi0", "msi1", "msi2", "msi3",
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"msi4", "msi5", "msi6", "msi7",
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"msi8", "msi9", "msi10", "msi11",
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"msi12", "msi13", "msi14", "msi15",
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"legacy";
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status = "disabled";
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};
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};
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};
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@ -779,7 +779,7 @@
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};
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replicator@fc31c000 {
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compatible = "qcom,coresight-replicator1x", "arm,primecell";
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compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
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reg = <0xfc31c000 0x1000>;
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clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
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