ARM: cache-l2x0: avoid taking spinlock for every iteration
Taking the spinlock for every iteration is very expensive; instead, batch iterations up into 4K blocks, releasing and reacquiring the spinlock between each block. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
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22763c5cf3
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0eb948dd7f
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@ -31,14 +31,10 @@ static DEFINE_SPINLOCK(l2x0_lock);
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static inline void sync_writel(unsigned long val, unsigned long reg,
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unsigned long complete_mask)
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{
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unsigned long flags;
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spin_lock_irqsave(&l2x0_lock, flags);
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writel(val, l2x0_base + reg);
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/* wait for the operation to complete */
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while (readl(l2x0_base + reg) & complete_mask)
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;
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static inline void cache_sync(void)
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@ -48,15 +44,20 @@ static inline void cache_sync(void)
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static inline void l2x0_inv_all(void)
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{
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unsigned long flags;
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/* invalidate all ways */
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spin_lock_irqsave(&l2x0_lock, flags);
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sync_writel(0xff, L2X0_INV_WAY, 0xff);
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_inv_range(unsigned long start, unsigned long end)
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{
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unsigned long addr;
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unsigned long flags;
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spin_lock_irqsave(&l2x0_lock, flags);
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if (start & (CACHE_LINE_SIZE - 1)) {
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start &= ~(CACHE_LINE_SIZE - 1);
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sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1);
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@ -68,29 +69,67 @@ static void l2x0_inv_range(unsigned long start, unsigned long end)
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sync_writel(end, L2X0_CLEAN_INV_LINE_PA, 1);
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}
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for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
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sync_writel(addr, L2X0_INV_LINE_PA, 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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sync_writel(start, L2X0_INV_LINE_PA, 1);
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start += CACHE_LINE_SIZE;
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}
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if (blk_end < end) {
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spin_unlock_irqrestore(&l2x0_lock, flags);
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spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_clean_range(unsigned long start, unsigned long end)
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{
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unsigned long addr;
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unsigned long flags;
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spin_lock_irqsave(&l2x0_lock, flags);
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start &= ~(CACHE_LINE_SIZE - 1);
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for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
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sync_writel(addr, L2X0_CLEAN_LINE_PA, 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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sync_writel(start, L2X0_CLEAN_LINE_PA, 1);
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start += CACHE_LINE_SIZE;
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}
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if (blk_end < end) {
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spin_unlock_irqrestore(&l2x0_lock, flags);
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spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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static void l2x0_flush_range(unsigned long start, unsigned long end)
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{
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unsigned long addr;
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unsigned long flags;
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spin_lock_irqsave(&l2x0_lock, flags);
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start &= ~(CACHE_LINE_SIZE - 1);
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for (addr = start; addr < end; addr += CACHE_LINE_SIZE)
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sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1);
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while (start < end) {
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unsigned long blk_end = start + min(end - start, 4096UL);
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while (start < blk_end) {
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sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1);
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start += CACHE_LINE_SIZE;
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}
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if (blk_end < end) {
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spin_unlock_irqrestore(&l2x0_lock, flags);
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spin_lock_irqsave(&l2x0_lock, flags);
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}
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}
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cache_sync();
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spin_unlock_irqrestore(&l2x0_lock, flags);
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}
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void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)
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