media: ccs: Fix the op_pll_multiplier address
According to the CCS spec the op_pll_multiplier address is 0x030e,
not 0x031e.
Signed-off-by: Bernhard Wimmer <be.wimm@gmail.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Cc: stable@vger.kernel.org
Fixes: 6493c4b777
("media: smiapp: Import CCS definitions")
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
This commit is contained in:
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caad794050
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// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
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/* Copyright (C) 2019--2020 Intel Corporation */
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/*
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* Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
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* do not modify.
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*/
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#include "ccs-limits.h"
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#include "ccs-regs.h"
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
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/* Copyright (C) 2019--2020 Intel Corporation */
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/*
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* Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
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* do not modify.
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*/
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#ifndef __CCS_LIMITS_H__
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#define __CCS_LIMITS_H__
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@ -1,5 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
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/* Copyright (C) 2019--2020 Intel Corporation */
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/*
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* Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
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* do not modify.
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*/
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#ifndef __CCS_REGS_H__
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#define __CCS_REGS_H__
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@ -202,7 +206,7 @@
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#define CCS_R_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT)
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#define CCS_R_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT)
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#define CCS_R_OP_PRE_PLL_CLK_DIV (0x030c | CCS_FL_16BIT)
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#define CCS_R_OP_PLL_MULTIPLIER (0x031e | CCS_FL_16BIT)
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#define CCS_R_OP_PLL_MULTIPLIER (0x030e | CCS_FL_16BIT)
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#define CCS_R_PLL_MODE 0x0310
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#define CCS_PLL_MODE_SHIFT 0U
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#define CCS_PLL_MODE_MASK 0x1
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