Second set of device tree changes for omaps for v4.13 merge
window: - Updates for droid 4 proximity sensor, WLAN and battery - Configure clocks for remoteproc devices for omap5 and dra7 - Configure omap4 crypto accelerators -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAllBDgARHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXMInQ/+JvCBrRUpNgv8MiGeD+tVXJ4Et5UN12IH ckReIcd9c3VZ/l88T0004BTZJl9RgZcQPrNG/JzUqka2tO2h5D7w3DBosNvL9AQm EH1KNMgHbqkU8mF+Qj+9feVMiFLG04VpYa2DAnuAVMeA5dFRSMcM/7CWXkrLr++N mT6ef+cB1X7Sn+A0Cl8v88axPAGqwwuD0x6BtP81keHN3O6He/Gz/BhSbsK6GHZs +5CeBrtRyT6NCmPS0bylLP/kDjIppDQpAFz0g1G016MEkmgmjzS77YqhXW6OyIBT anwQjPWBMe4QHuoNH/Yw6cwT5c2jrw5ZLArrZNqQmV+96UaQb5oF5KxVoqW4wd0E HZbl+GMDXeKXq0JBAQmtIHO7w2DTfeMxB9PFRaS1U7XVclmeN2svNpw8HSGFwIfb 5ll9I+BbgyV2BuryK904wry3GoFpU0pQw4o6qHTuiQlC59Nf7p9d2h5M3jQUIVBe YvizJhzoLRbmKAlA2xd1DL9eQUryiLOwrot1l8oWny1s1s33pKNw9DzV4Aa2r9O1 W2FyG05VgqROeu6Vt+Jpk+HYe+CzvgsONSnvGA/dd6HQQ1+SmRuF6xp40giPjZv4 ALpzUL8SaZWmJgmSDjYDHIqA5su/rJsR7puNHBj6/e/P0XPZbEGg+pZd3X7abwe5 7corDCcSatc= =3V8K -----END PGP SIGNATURE----- Merge tag 'omap-for-v4.13/dt-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Second set of device tree changes for omaps for v4.13 merge window: - Updates for droid 4 proximity sensor, WLAN and battery - Configure clocks for remoteproc devices for omap5 and dra7 - Configure omap4 crypto accelerators * tag 'omap-for-v4.13/dt-part2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: dts: omap4: add SHAM node ARM: dts: omap4: add aes2 instance ARM: dts: omap4.dtsi: remove aes[12]_fck ARM: dts: omap4: Fix aes entry ARM: dts: omap4-droid4: Configure CPCAP battery driver ARM: dts: dra7xx-clocks: Use DPLL_GPU for GPU clocks ARM: dts: dra7xx-clocks: Set IVA DPLL and its output clock rates ARM: dts: dra7xx-clocks: Set DSP DPLL and its output clock rates ARM: dts: dra7xx-clocks: Source IPU1 functional clock from CORE DPLL ARM: dts: omap54xx-clocks: Set IVA DPLL and its output clock rates ARM: dts: omap44xx-clocks: Set IVA DPLL and its output clock rates ARM: dts: omap4-droid4: Fix WLAN compatible ARM: dts: omap4-droid4: Add isl29030 ALS/proximity sensor Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
0d817768c0
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@ -338,6 +338,8 @@
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compatible = "ti,omap4-dpll-clock";
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clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
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reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
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assigned-clocks = <&dpll_dsp_ck>;
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assigned-clock-rates = <600000000>;
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};
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dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
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@ -349,6 +351,8 @@
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reg = <0x0244>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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assigned-clocks = <&dpll_dsp_m2_ck>;
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assigned-clock-rates = <600000000>;
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};
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iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
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@ -372,6 +376,8 @@
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compatible = "ti,omap4-dpll-clock";
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clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
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reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
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assigned-clocks = <&dpll_iva_ck>;
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assigned-clock-rates = <1165000000>;
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};
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dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
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@ -383,6 +389,8 @@
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reg = <0x01b0>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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assigned-clocks = <&dpll_iva_m2_ck>;
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assigned-clock-rates = <388333334>;
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};
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iva_dclk: iva_dclk {
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@ -406,6 +414,8 @@
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compatible = "ti,omap4-dpll-clock";
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clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
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reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
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assigned-clocks = <&dpll_gpu_ck>;
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assigned-clock-rates = <1277000000>;
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};
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dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
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@ -417,6 +427,8 @@
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reg = <0x02e8>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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assigned-clocks = <&dpll_gpu_m2_ck>;
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assigned-clock-rates = <425666667>;
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};
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dpll_core_m2_ck: dpll_core_m2_ck@130 {
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@ -659,6 +671,8 @@
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reg = <0x0248>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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assigned-clocks = <&dpll_dsp_m3x2_ck>;
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assigned-clock-rates = <400000000>;
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};
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dpll_gmac_x2_ck: dpll_gmac_x2_ck {
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@ -791,6 +805,8 @@
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clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
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ti,bit-shift = <24>;
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reg = <0x0520>;
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assigned-clocks = <&ipu1_gfclk_mux>;
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assigned-clock-parents = <&dpll_core_h22x2_ck>;
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};
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mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
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@ -1748,6 +1764,8 @@
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clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
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ti,bit-shift = <24>;
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reg = <0x1220>;
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assigned-clocks = <&gpu_core_gclk_mux>;
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assigned-clock-parents = <&dpll_gpu_m2_ck>;
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};
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gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
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@ -1756,6 +1774,8 @@
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clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
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ti,bit-shift = <26>;
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reg = <0x1220>;
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assigned-clocks = <&gpu_hyd_gclk_mux>;
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assigned-clock-parents = <&dpll_gpu_m2_ck>;
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};
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l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
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@ -26,6 +26,22 @@
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#io-channel-cells = <1>;
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};
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cpcap_battery: battery {
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compatible = "motorola,cpcap-battery";
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interrupts-extended = <
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&cpcap 6 0 &cpcap 5 0 &cpcap 3 0
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&cpcap 20 0 &cpcap 54 0
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>;
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interrupt-names =
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"eol", "lowbph", "lowbpl",
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"chrgcurr1", "battdetb";
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io-channels = <&cpcap_adc 0 &cpcap_adc 1
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&cpcap_adc 5 &cpcap_adc 6>;
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io-channel-names = "battdetb", "battp",
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"chg_isense", "batti";
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power-supplies = <&cpcap_charger>;
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};
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cpcap_charger: charger {
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compatible = "motorola,mapphone-cpcap-charger";
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interrupts-extended = <
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@ -301,7 +301,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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wlcore: wlcore@2 {
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compatible = "ti,wl1283";
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compatible = "ti,wl1285", "ti,wl1283";
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reg = <2>;
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interrupt-parent = <&gpio4>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; /* gpio100 */
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@ -348,6 +348,17 @@
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interrupt-names = "irq", "wakeup";
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wakeup-source;
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};
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isl29030@44 {
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compatible = "isil,isl29030";
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reg = <0x44>;
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pinctrl-names = "default";
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pinctrl-0 = <&als_proximity_pins>;
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interrupt-parent = <&gpio6>;
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interrupts = <17 IRQ_TYPE_LEVEL_LOW>; /* gpio177 */
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};
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};
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&omap4_pmx_core {
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@ -395,6 +406,12 @@
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>;
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};
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als_proximity_pins: pinmux_als_proximity_pins {
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pinctrl-single,pins = <
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OMAP4_IOPAD(0x18c, PIN_INPUT_PULLUP | MUX_MODE3)
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>;
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};
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usb_ulpi_pins: pinmux_usb_ulpi_pins {
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pinctrl-single,pins = <
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OMAP4_IOPAD(0x196, MUX_MODE7)
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@ -900,15 +900,24 @@
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ctrl-module = <&omap_control_usbotg>;
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};
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aes: aes@4b501000 {
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aes1: aes@4b501000 {
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compatible = "ti,omap4-aes";
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ti,hwmods = "aes";
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ti,hwmods = "aes1";
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reg = <0x4b501000 0xa0>;
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 111>, <&sdma 110>;
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dma-names = "tx", "rx";
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};
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aes2: aes@4b701000 {
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compatible = "ti,omap4-aes";
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ti,hwmods = "aes2";
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reg = <0x4b701000 0xa0>;
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interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 114>, <&sdma 113>;
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dma-names = "tx", "rx";
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};
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des: des@480a5000 {
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compatible = "ti,omap4-des";
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ti,hwmods = "des";
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@ -918,6 +927,15 @@
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dma-names = "tx", "rx";
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};
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sham: sham@4b100000 {
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compatible = "ti,omap4-sham";
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ti,hwmods = "sham";
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reg = <0x4b100000 0x300>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&sdma 119>;
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dma-names = "rx";
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};
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abb_mpu: regulator-abb-mpu {
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compatible = "ti,abb-v2";
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regulator-name = "abb_mpu";
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@ -357,6 +357,8 @@
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compatible = "ti,omap4-dpll-clock";
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clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
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reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
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assigned-clocks = <&dpll_iva_ck>;
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assigned-clock-rates = <931200000>;
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};
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dpll_iva_x2_ck: dpll_iva_x2_ck {
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@ -374,6 +376,8 @@
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reg = <0x01b8>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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assigned-clocks = <&dpll_iva_m4x2_ck>;
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assigned-clock-rates = <465600000>;
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};
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dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
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@ -385,6 +389,8 @@
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reg = <0x01bc>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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assigned-clocks = <&dpll_iva_m5x2_ck>;
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assigned-clock-rates = <266100000>;
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};
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dpll_mpu_ck: dpll_mpu_ck@160 {
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@ -969,22 +975,6 @@
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ti,max-div = <2>;
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};
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aes1_fck: aes1_fck@15a0 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3_div_ck>;
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ti,bit-shift = <1>;
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reg = <0x15a0>;
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};
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aes2_fck: aes2_fck@15a8 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&l3_div_ck>;
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ti,bit-shift = <1>;
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reg = <0x15a8>;
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};
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dss_sys_clk: dss_sys_clk@1120 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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@ -315,6 +315,8 @@
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compatible = "ti,omap4-dpll-clock";
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clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
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reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
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assigned-clocks = <&dpll_iva_ck>;
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assigned-clock-rates = <1165000000>;
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};
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dpll_iva_x2_ck: dpll_iva_x2_ck {
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@ -330,6 +332,8 @@
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ti,max-div = <63>;
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reg = <0x01b8>;
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ti,index-starts-at-one;
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assigned-clocks = <&dpll_iva_h11x2_ck>;
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assigned-clock-rates = <465920000>;
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};
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dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
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@ -339,6 +343,8 @@
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ti,max-div = <63>;
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reg = <0x01bc>;
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ti,index-starts-at-one;
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assigned-clocks = <&dpll_iva_h12x2_ck>;
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assigned-clock-rates = <388300000>;
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};
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mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
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