drm/i915: Move GT registers to their own header file

This is a huge, chaotic mass of registers copied over as-is without any
real cleanup.  We'll come back and organize these better, align on
consistent coding style, remove dead code, etc. in separate patches
later that will be easier to review.

v2:
 - Add missing include in intel_pxp_irq.c
v3:
 - Correct a few indentation errors (Lucas)
 - Minor conflict resolution

Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220127234334.4016964-6-matthew.d.roper@intel.com

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

@@ -7,8 +7,9 @@
 
 #include "gt/intel_context.h"
 #include "gt/intel_engine_user.h"
-#include "gt/intel_gt.h"
 #include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt.h"
+#include "gt/intel_gt_regs.h"
 #include "gem/i915_gem_lmem.h"
 
 #include "selftests/igt_flush_test.h"

drivers/gpu/drm/i915/gt/gen6_ppgtt.c

@@ -9,6 +9,7 @@
 #include "i915_scatterlist.h"
 #include "i915_trace.h"
 #include "i915_vgpu.h"
+#include "intel_gt_regs.h"
 #include "intel_engine_regs.h"
 #include "intel_gt.h"
 

drivers/gpu/drm/i915/gt/gen7_renderclear.c

@@ -6,6 +6,7 @@
 #include "gen7_renderclear.h"
 #include "i915_drv.h"
 #include "intel_gpu_commands.h"
+#include "intel_gt_regs.h"
 
 #define GT3_INLINE_DATA_DELAYS 0x1E00
 #define batch_advance(Y, CS) GEM_BUG_ON((Y)->end != (CS))

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

@@ -5,8 +5,9 @@
 
 #include "gen8_engine_cs.h"
 #include "i915_drv.h"
-#include "intel_lrc.h"
 #include "intel_gpu_commands.h"
+#include "intel_gt_regs.h"
+#include "intel_lrc.h"
 #include "intel_ring.h"
 
 int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)

drivers/gpu/drm/i915/gt/intel_engine_cs.c

@@ -6,6 +6,7 @@
 #include <drm/drm_print.h>
 
 #include "gem/i915_gem_context.h"
+#include "gt/intel_gt_regs.h"
 
 #include "i915_cmd_parser.h"
 #include "i915_drv.h"

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

@@ -122,6 +122,7 @@
 #include "intel_gt.h"
 #include "intel_gt_irq.h"
 #include "intel_gt_pm.h"
+#include "intel_gt_regs.h"
 #include "intel_gt_requests.h"
 #include "intel_lrc.h"
 #include "intel_lrc_reg.h"

drivers/gpu/drm/i915/gt/intel_ggtt.c

@@ -15,6 +15,7 @@
 #include "gem/i915_gem_lmem.h"
 
 #include "intel_gt.h"
+#include "intel_gt_regs.h"
 #include "i915_drv.h"
 #include "i915_scatterlist.h"
 #include "i915_vgpu.h"

drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c

@@ -7,6 +7,7 @@
 #include "i915_scatterlist.h"
 #include "i915_pvinfo.h"
 #include "i915_vgpu.h"
+#include "intel_gt_regs.h"
 
 /**
  * DOC: fence register handling

drivers/gpu/drm/i915/gt/intel_gt.c

@@ -15,6 +15,7 @@
 #include "intel_gt_buffer_pool.h"
 #include "intel_gt_clock_utils.h"
 #include "intel_gt_pm.h"
+#include "intel_gt_regs.h"
 #include "intel_gt_requests.h"
 #include "intel_migrate.h"
 #include "intel_mocs.h"

drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c

@@ -6,6 +6,7 @@
 #include "i915_drv.h"
 #include "intel_gt.h"
 #include "intel_gt_clock_utils.h"
+#include "intel_gt_regs.h"
 
 static u32 read_reference_ts_freq(struct intel_uncore *uncore)
 {

drivers/gpu/drm/i915/gt/intel_gt_irq.c

@@ -10,7 +10,7 @@
 #include "intel_breadcrumbs.h"
 #include "intel_gt.h"
 #include "intel_gt_irq.h"
-#include "intel_lrc_reg.h"
+#include "intel_gt_regs.h"
 #include "intel_uncore.h"
 #include "intel_rps.h"
 #include "pxp/intel_pxp_irq.h"

drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c

@@ -12,6 +12,7 @@
 #include "intel_gt_debugfs.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_pm_debugfs.h"
+#include "intel_gt_regs.h"
 #include "intel_llc.h"
 #include "intel_pcode.h"
 #include "intel_rc6.h"

drivers/gpu/drm/i915/gt/intel_gt_pm_irq.c

@@ -8,6 +8,7 @@
 #include "intel_gt.h"
 #include "intel_gt_irq.h"
 #include "intel_gt_pm_irq.h"
+#include "intel_gt_regs.h"
 
 static void write_pm_imr(struct intel_gt *gt)
 {

drivers/gpu/drm/i915/gt/intel_gtt.c

@@ -13,6 +13,7 @@
 #include "gem/i915_gem_lmem.h"
 #include "i915_trace.h"
 #include "intel_gt.h"
+#include "intel_gt_regs.h"
 #include "intel_gtt.h"
 
 struct drm_i915_gem_object *alloc_pt_lmem(struct i915_address_space *vm, int sz)

drivers/gpu/drm/i915/gt/intel_lrc.c

@@ -12,6 +12,7 @@
 #include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
+#include "intel_gt_regs.h"
 #include "intel_lrc.h"
 #include "intel_lrc_reg.h"
 #include "intel_ring.h"

drivers/gpu/drm/i915/gt/intel_mocs.c

@@ -7,7 +7,7 @@
 
 #include "intel_engine.h"
 #include "intel_gt.h"
-#include "intel_lrc_reg.h"
+#include "intel_gt_regs.h"
 #include "intel_mocs.h"
 #include "intel_ring.h"
 

drivers/gpu/drm/i915/gt/intel_rc6.c

@@ -10,6 +10,7 @@
 #include "intel_engine_regs.h"
 #include "intel_gt.h"
 #include "intel_gt_pm.h"
+#include "intel_gt_regs.h"
 #include "intel_pcode.h"
 #include "intel_rc6.h"
 

drivers/gpu/drm/i915/gt/intel_reset.c

@@ -11,6 +11,8 @@
 
 #include "gem/i915_gem_context.h"
 
+#include "gt/intel_gt_regs.h"
+
 #include "i915_drv.h"
 #include "i915_gpu_error.h"
 #include "i915_irq.h"

drivers/gpu/drm/i915/gt/intel_ring_submission.c

@@ -14,6 +14,7 @@
 #include "intel_engine_regs.h"
 #include "intel_gt.h"
 #include "intel_gt_irq.h"
+#include "intel_gt_regs.h"
 #include "intel_reset.h"
 #include "intel_ring.h"
 #include "shmem_utils.h"

drivers/gpu/drm/i915/gt/intel_rps.c

@@ -12,6 +12,7 @@
 #include "intel_gt_clock_utils.h"
 #include "intel_gt_irq.h"
 #include "intel_gt_pm_irq.h"
+#include "intel_gt_regs.h"
 #include "intel_pcode.h"
 #include "intel_rps.h"
 #include "vlv_sideband.h"

drivers/gpu/drm/i915/gt/intel_sseu.c

@@ -5,6 +5,7 @@
 
 #include "i915_drv.h"
 #include "intel_engine_regs.h"
+#include "intel_gt_regs.h"
 #include "intel_sseu.h"
 
 void intel_sseu_set_info(struct sseu_dev_info *sseu, u8 max_slices,

drivers/gpu/drm/i915/gt/intel_sseu_debugfs.c

@@ -6,6 +6,7 @@
 
 #include "i915_drv.h"
 #include "intel_gt_debugfs.h"
+#include "intel_gt_regs.h"
 #include "intel_sseu_debugfs.h"
 
 static void sseu_copy_subslices(const struct sseu_dev_info *sseu,

drivers/gpu/drm/i915/gt/intel_workarounds.c

@@ -9,6 +9,7 @@
 #include "intel_engine_regs.h"
 #include "intel_gpu_commands.h"
 #include "intel_gt.h"
+#include "intel_gt_regs.h"
 #include "intel_ring.h"
 #include "intel_workarounds.h"
 

drivers/gpu/drm/i915/gt/uc/intel_guc.c

@@ -7,6 +7,7 @@
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_irq.h"
 #include "gt/intel_gt_pm_irq.h"
+#include "gt/intel_gt_regs.h"
 #include "intel_guc.h"
 #include "intel_guc_slpc.h"
 #include "intel_guc_ads.h"

drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c

@@ -7,6 +7,7 @@
 
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_lrc.h"
 #include "gt/shmem_utils.h"
 #include "intel_guc_ads.h"

drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c

@@ -10,6 +10,7 @@
  */
 
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_regs.h"
 #include "intel_guc_fw.h"
 #include "i915_drv.h"
 

drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c

@@ -6,6 +6,7 @@
 #include "i915_drv.h"
 #include "intel_guc_slpc.h"
 #include "gt/intel_gt.h"
+#include "gt/intel_gt_regs.h"
 
 static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
 {

drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c

@@ -17,6 +17,7 @@
 #include "gt/intel_gt_clock_utils.h"
 #include "gt/intel_gt_irq.h"
 #include "gt/intel_gt_pm.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_gt_requests.h"
 #include "gt/intel_lrc.h"
 #include "gt/intel_lrc_reg.h"

drivers/gpu/drm/i915/gvt/cmd_parser.c

@@ -39,6 +39,7 @@
 #include "i915_drv.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_lrc.h"
 #include "gt/intel_ring.h"
 #include "gt/intel_gt_requests.h"

drivers/gpu/drm/i915/gvt/gtt.c

@@ -38,6 +38,8 @@
 #include "i915_pvinfo.h"
 #include "trace.h"
 
+#include "gt/intel_gt_regs.h"
+
 #if defined(VERBOSE_DEBUG)
 #define gvt_vdbg_mm(fmt, args...) gvt_dbg_mm(fmt, ##args)
 #else

drivers/gpu/drm/i915/gvt/handlers.c

@@ -41,6 +41,7 @@
 #include "i915_pvinfo.h"
 #include "display/intel_display_types.h"
 #include "display/intel_fbc.h"
+#include "gt/intel_gt_regs.h"
 
 /* XXX FIXME i915 has changed PP_XXX definition */
 #define PCH_PP_STATUS  _MMIO(0xc7200)

drivers/gpu/drm/i915/gvt/mmio.c

@@ -36,6 +36,8 @@
 #include "i915_drv.h"
 #include "gvt.h"
 
+#include "gt/intel_gt_regs.h"
+
 /**
  * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
  * @vgpu: a vGPU

drivers/gpu/drm/i915/gvt/mmio_context.c

@@ -37,6 +37,7 @@
 #include "gt/intel_context.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_ring.h"
 #include "gvt.h"
 #include "trace.h"

drivers/gpu/drm/i915/gvt/scheduler.c

@@ -38,6 +38,7 @@
 #include "gem/i915_gem_pm.h"
 #include "gt/intel_context.h"
 #include "gt/intel_execlists_submission.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_lrc.h"
 #include "gt/intel_ring.h"
 

drivers/gpu/drm/i915/i915_cmd_parser.c

@@ -28,6 +28,7 @@
 #include "gt/intel_engine.h"
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gpu_commands.h"
+#include "gt/intel_gt_regs.h"
 
 #include "i915_cmd_parser.h"
 #include "i915_drv.h"

drivers/gpu/drm/i915/i915_debugfs.c

@@ -38,6 +38,7 @@
 #include "gt/intel_gt_debugfs.h"
 #include "gt/intel_gt_pm.h"
 #include "gt/intel_gt_pm_debugfs.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_gt_requests.h"
 #include "gt/intel_rc6.h"
 #include "gt/intel_reset.h"

drivers/gpu/drm/i915/i915_gpu_error.c

@@ -44,6 +44,7 @@
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_pm.h"
+#include "gt/intel_gt_regs.h"
 
 #include "i915_drv.h"
 #include "i915_gpu_error.h"

drivers/gpu/drm/i915/i915_irq.c

@@ -46,6 +46,7 @@
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_irq.h"
 #include "gt/intel_gt_pm_irq.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_rps.h"
 
 #include "i915_drv.h"

drivers/gpu/drm/i915/i915_perf.c

@@ -203,6 +203,7 @@
 #include "gt/intel_gpu_commands.h"
 #include "gt/intel_gt.h"
 #include "gt/intel_gt_clock_utils.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_lrc.h"
 #include "gt/intel_ring.h"
 

drivers/gpu/drm/i915/i915_pmu.c

@@ -11,6 +11,7 @@
 #include "gt/intel_engine_regs.h"
 #include "gt/intel_engine_user.h"
 #include "gt/intel_gt_pm.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_rc6.h"
 #include "gt/intel_rps.h"
 

drivers/gpu/drm/i915/i915_sysfs.c

@@ -30,6 +30,7 @@
 #include <linux/stat.h>
 #include <linux/sysfs.h>
 
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_rc6.h"
 #include "gt/intel_rps.h"
 #include "gt/sysfs_engines.h"

drivers/gpu/drm/i915/intel_pm.c

@@ -44,6 +44,7 @@
 #include "display/skl_universal_plane.h"
 
 #include "gt/intel_engine_regs.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_llc.h"
 
 #include "i915_drv.h"

drivers/gpu/drm/i915/intel_uncore.c

@@ -24,6 +24,7 @@
 #include <linux/pm_runtime.h>
 
 #include "gt/intel_engine_regs.h"
+#include "gt/intel_gt_regs.h"
 
 #include "i915_drv.h"
 #include "i915_iosf_mbi.h"

drivers/gpu/drm/i915/pxp/intel_pxp_irq.c

@@ -7,6 +7,7 @@
 #include "intel_pxp_irq.h"
 #include "intel_pxp_session.h"
 #include "gt/intel_gt_irq.h"
+#include "gt/intel_gt_regs.h"
 #include "gt/intel_gt_types.h"
 #include "i915_irq.h"
 #include "i915_reg.h"

drivers/gpu/drm/i915/vlv_suspend.c

@@ -14,6 +14,8 @@
 #include "intel_pm.h"
 #include "vlv_suspend.h"
 
+#include "gt/intel_gt_regs.h"
+
 struct vlv_s0ix_state {
 	/* GAM */
 	u32 wr_watermark;