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ARM: mvebu: Fix the operand list in the inline asm of armada_370_xp_pmsu_idle_enter 

In the inline asm part of the function armada_370_xp_pmsu_idle_enter()
the input operand was used. The intent here was to let the compiler
choose this register so it could do the optimization it
needed.

However an input operand is not supposed to be modified by the inline
asm code. This can lead to improper generated instructions.

In some case generated instruction the compiler made the choice to
reuse the same register to store the return value. But in the assembly
part this register was modified, so it can lead to return an wrong
value.

The fix is to use a clobber. Thanks to this the compiler will know
that the value of this register will be modified.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1404483736-16938-1-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Gregory CLEMENT 2014-07-04 16:22:16 +02:00 committed by Jason Cooper
parent 0e2be4c112
commit 0d461e1b08
1 changed files with 5 additions and 5 deletions
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10
arch/arm/mach-mvebu/pmsu.c
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@ -201,12 +201,12 @@ static noinline int do_armada_370_xp_cpu_suspend(unsigned long deepidle)
/* Test the CR_C bit and set it if it was cleared */ /* Test the CR_C bit and set it if it was cleared */
asm volatile( asm volatile(
"mrc p15, 0, %0, c1, c0, 0 \n\t" "mrc p15, 0, r0, c1, c0, 0 \n\t"
"tst %0, #(1 << 2) \n\t" "tst r0, #(1 << 2) \n\t"
"orreq %0, %0, #(1 << 2) \n\t" "orreq r0, r0, #(1 << 2) \n\t"
"mcreq p15, 0, %0, c1, c0, 0 \n\t" "mcreq p15, 0, r0, c1, c0, 0 \n\t"
"isb " "isb "
: : "r" (0)); : : : "r0");
pr_warn("Failed to suspend the system\n"); pr_warn("Failed to suspend the system\n");