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MIPS: Octeon: Delete legacy code for PHY access 

PHY access through the board helper is impossible with the
current drivers, so delete this code.

Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Cc: David Daney <ddaney@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/14205/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Aaro Koskinen 2016-09-02 23:44:20 +03:00 committed by Ralf Baechle
parent 0a1e192d66
commit 0d19672e78
1 changed files with 2 additions and 106 deletions
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108
arch/mips/cavium-octeon/executive/cvmx-helper-board.c
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@ -211,8 +211,6 @@ int cvmx_helper_board_get_mii_address(int ipd_port)
cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
{
cvmx_helper_link_info_t result;
int phy_addr;
int is_broadcom_phy = 0;
/* Unless we fix it later, all links are defaulted to down */
result.u64 = 0;
@ -248,8 +246,7 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
result.s.full_duplex = 1;
result.s.speed = 1000;
return result;
} else /* The other port uses a broadcom PHY */
is_broadcom_phy = 1;
}
break;
case CVMX_BOARD_TYPE_BBGW_REF:
/* Port 1 on these boards is always Gigabit */
@ -267,108 +264,7 @@ cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port)
break;
}
phy_addr = cvmx_helper_board_get_mii_address(ipd_port);
if (phy_addr != -1) {
if (is_broadcom_phy) {
/*
* Below we are going to read SMI/MDIO
* register 0x19 which works on Broadcom
* parts
*/
int phy_status =
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff,
0x19);
switch ((phy_status >> 8) & 0x7) {
case 0:
result.u64 = 0;
break;
case 1:
result.s.link_up = 1;
result.s.full_duplex = 0;
result.s.speed = 10;
break;
case 2:
result.s.link_up = 1;
result.s.full_duplex = 1;
result.s.speed = 10;
break;
case 3:
result.s.link_up = 1;
result.s.full_duplex = 0;
result.s.speed = 100;
break;
case 4:
result.s.link_up = 1;
result.s.full_duplex = 1;
result.s.speed = 100;
break;
case 5:
result.s.link_up = 1;
result.s.full_duplex = 1;
result.s.speed = 100;
break;
case 6:
result.s.link_up = 1;
result.s.full_duplex = 0;
result.s.speed = 1000;
break;
case 7:
result.s.link_up = 1;
result.s.full_duplex = 1;
result.s.speed = 1000;
break;
}
} else {
/*
* This code assumes we are using a Marvell
* Gigabit PHY. All the speed information can
* be read from register 17 in one
* go. Somebody using a different PHY will
* need to handle it above in the board
* specific area.
*/
int phy_status =
cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17);
/*
* If the resolve bit 11 isn't set, see if
* autoneg is turned off (bit 12, reg 0). The
* resolve bit doesn't get set properly when
* autoneg is off, so force it.
*/
if ((phy_status & (1 << 11)) == 0) {
int auto_status =
cvmx_mdio_read(phy_addr >> 8,
phy_addr & 0xff, 0);
if ((auto_status & (1 << 12)) == 0)
phy_status |= 1 << 11;
}
/*
* Only return a link if the PHY has finished
* auto negotiation and set the resolved bit
* (bit 11)
*/
if (phy_status & (1 << 11)) {
result.s.link_up = 1;
result.s.full_duplex = ((phy_status >> 13) & 1);
switch ((phy_status >> 14) & 3) {
case 0: /* 10 Mbps */
result.s.speed = 10;
break;
case 1: /* 100 Mbps */
result.s.speed = 100;
break;
case 2: /* 1 Gbps */
result.s.speed = 1000;
break;
case 3: /* Illegal */
result.u64 = 0;
break;
}
}
}
} else if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
if (OCTEON_IS_MODEL(OCTEON_CN3XXX)
|| OCTEON_IS_MODEL(OCTEON_CN58XX)
|| OCTEON_IS_MODEL(OCTEON_CN50XX)) {
/*