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arm64: dts: ti: k3-j7200: fix main pinmux range 

Range size of 0x2b4 was incorrect since there isn't 173 configurable
pins for muxing. Additionally there is a non-addressable region in the
mapping which requires splitting into two ranges.

main_pmx0 -> 67 pins
main_pmx1 -> 3 pins

Fixes: d361ed8845 ("arm64: dts: ti: Add support for J7200 SoC")
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Vaishnav Achath <vaishnav.a@ti.com>
Link: https://lore.kernel.org/r/20220919205723.8342-1-mranostay@ti.com
This commit is contained in:
Matt Ranostay 2022-09-19 13:57:23 -07:00 committed by Vignesh Raghavendra
parent 38c4a08c82
commit 0d0a0b4413
2 changed files with 18 additions and 7 deletions
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14
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
View File

@ -134,12 +134,6 @@
>;
};
main_usbss0_pins_default: main-usbss0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
};
vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
@ -147,6 +141,14 @@
};
};
&main_pmx1 {
main_usbss0_pins_default: main-usbss0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
>;
};
};
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
status = "reserved";

11
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
View File

@ -295,7 +295,16 @@
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x11c000 0x00 0x2b4>;
reg = <0x00 0x11c000 0x00 0x10c>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
main_pmx1: pinctrl@11c11c {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
reg = <0x00 0x11c11c 0x00 0xc>;
#pinctrl-cells = <1>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;