i2c-algo-bit: Fix timeout test
When fetching DDC using i2c algo bit, we were often seeing timeouts before getting valid EDID on a retry. The VESA spec states 2ms is the DDC timeout, so when this translates into 1 jiffie and we are close to the end of the time period, it could return with a timeout less than 2ms. Change this code to use time_after instead of time_after_eq. Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Jean Delvare <khali@linux-fr.org>
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@ -104,7 +104,7 @@ static int sclhi(struct i2c_algo_bit_data *adap)
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* chips may hold it low ("clock stretching") while they
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* are processing data internally.
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*/
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if (time_after_eq(jiffies, start + adap->timeout))
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if (time_after(jiffies, start + adap->timeout))
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return -ETIMEDOUT;
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cond_resched();
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}
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