arm64: entry: Annotate vector table and handlers as code
In an effort to clarify and simplify the annotation of assembly functions new macros have been introduced. These replace ENTRY and ENDPROC with two different annotations for normal functions and those with unusual calling conventions. The vector table and handlers aren't normal C style code so should be annotated as CODE. Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -465,7 +465,7 @@ alternative_endif
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.pushsection ".entry.text", "ax"
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.align 11
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ENTRY(vectors)
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SYM_CODE_START(vectors)
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kernel_ventry 1, sync_invalid // Synchronous EL1t
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kernel_ventry 1, irq_invalid // IRQ EL1t
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kernel_ventry 1, fiq_invalid // FIQ EL1t
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@ -492,7 +492,7 @@ ENTRY(vectors)
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kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
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kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
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#endif
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END(vectors)
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SYM_CODE_END(vectors)
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#ifdef CONFIG_VMAP_STACK
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/*
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@ -534,57 +534,57 @@ __bad_stack:
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ASM_BUG()
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.endm
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el0_sync_invalid:
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SYM_CODE_START_LOCAL(el0_sync_invalid)
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inv_entry 0, BAD_SYNC
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ENDPROC(el0_sync_invalid)
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SYM_CODE_END(el0_sync_invalid)
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el0_irq_invalid:
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SYM_CODE_START_LOCAL(el0_irq_invalid)
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inv_entry 0, BAD_IRQ
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ENDPROC(el0_irq_invalid)
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SYM_CODE_END(el0_irq_invalid)
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el0_fiq_invalid:
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SYM_CODE_START_LOCAL(el0_fiq_invalid)
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inv_entry 0, BAD_FIQ
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ENDPROC(el0_fiq_invalid)
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SYM_CODE_END(el0_fiq_invalid)
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el0_error_invalid:
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SYM_CODE_START_LOCAL(el0_error_invalid)
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inv_entry 0, BAD_ERROR
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ENDPROC(el0_error_invalid)
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SYM_CODE_END(el0_error_invalid)
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#ifdef CONFIG_COMPAT
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el0_fiq_invalid_compat:
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SYM_CODE_START_LOCAL(el0_fiq_invalid_compat)
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inv_entry 0, BAD_FIQ, 32
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ENDPROC(el0_fiq_invalid_compat)
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SYM_CODE_END(el0_fiq_invalid_compat)
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#endif
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el1_sync_invalid:
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SYM_CODE_START_LOCAL(el1_sync_invalid)
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inv_entry 1, BAD_SYNC
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ENDPROC(el1_sync_invalid)
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SYM_CODE_END(el1_sync_invalid)
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el1_irq_invalid:
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SYM_CODE_START_LOCAL(el1_irq_invalid)
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inv_entry 1, BAD_IRQ
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ENDPROC(el1_irq_invalid)
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SYM_CODE_END(el1_irq_invalid)
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el1_fiq_invalid:
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SYM_CODE_START_LOCAL(el1_fiq_invalid)
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inv_entry 1, BAD_FIQ
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ENDPROC(el1_fiq_invalid)
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SYM_CODE_END(el1_fiq_invalid)
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el1_error_invalid:
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SYM_CODE_START_LOCAL(el1_error_invalid)
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inv_entry 1, BAD_ERROR
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ENDPROC(el1_error_invalid)
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SYM_CODE_END(el1_error_invalid)
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/*
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* EL1 mode handlers.
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*/
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.align 6
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el1_sync:
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SYM_CODE_START_LOCAL_NOALIGN(el1_sync)
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kernel_entry 1
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mov x0, sp
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bl el1_sync_handler
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kernel_exit 1
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ENDPROC(el1_sync)
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SYM_CODE_END(el1_sync)
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.align 6
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el1_irq:
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SYM_CODE_START_LOCAL_NOALIGN(el1_irq)
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kernel_entry 1
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gic_prio_irq_setup pmr=x20, tmp=x1
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enable_da_f
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@ -639,42 +639,42 @@ alternative_else_nop_endif
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#endif
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kernel_exit 1
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ENDPROC(el1_irq)
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SYM_CODE_END(el1_irq)
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/*
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* EL0 mode handlers.
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*/
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.align 6
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el0_sync:
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SYM_CODE_START_LOCAL_NOALIGN(el0_sync)
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kernel_entry 0
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mov x0, sp
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bl el0_sync_handler
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b ret_to_user
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ENDPROC(el0_sync)
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SYM_CODE_END(el0_sync)
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#ifdef CONFIG_COMPAT
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.align 6
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el0_sync_compat:
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SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat)
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kernel_entry 0, 32
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mov x0, sp
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bl el0_sync_compat_handler
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b ret_to_user
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ENDPROC(el0_sync_compat)
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SYM_CODE_END(el0_sync_compat)
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.align 6
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el0_irq_compat:
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SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat)
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kernel_entry 0, 32
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b el0_irq_naked
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ENDPROC(el0_irq_compat)
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SYM_CODE_END(el0_irq_compat)
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el0_error_compat:
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SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat)
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kernel_entry 0, 32
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b el0_error_naked
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ENDPROC(el0_error_compat)
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SYM_CODE_END(el0_error_compat)
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#endif
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.align 6
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el0_irq:
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SYM_CODE_START_LOCAL_NOALIGN(el0_irq)
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kernel_entry 0
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el0_irq_naked:
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gic_prio_irq_setup pmr=x20, tmp=x0
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@ -696,9 +696,9 @@ el0_irq_naked:
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bl trace_hardirqs_on
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#endif
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b ret_to_user
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ENDPROC(el0_irq)
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SYM_CODE_END(el0_irq)
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el1_error:
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SYM_CODE_START_LOCAL(el1_error)
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kernel_entry 1
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mrs x1, esr_el1
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gic_prio_kentry_setup tmp=x2
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@ -706,9 +706,9 @@ el1_error:
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mov x0, sp
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bl do_serror
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kernel_exit 1
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ENDPROC(el1_error)
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SYM_CODE_END(el1_error)
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el0_error:
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SYM_CODE_START_LOCAL(el0_error)
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kernel_entry 0
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el0_error_naked:
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mrs x25, esr_el1
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@ -720,7 +720,7 @@ el0_error_naked:
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bl do_serror
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enable_da_f
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b ret_to_user
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ENDPROC(el0_error)
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SYM_CODE_END(el0_error)
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/*
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* Ok, we need to do extra processing, enter the slow path.
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