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drm/amd/display: implement edid max TMDS clock check in DC 

[WHY]
Currently DC doesn't check requested pixel clock against an EDID
specified TMDS max clock if it exists, passing modes that should fail

[HOW]
Add max TMDS clk to edid caps and perform check during validation

Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Michael Strauss 2020-05-26 17:09:31 -04:00 committed by Alex Deucher
parent a85f148ed3
commit 0cc722248a
2 changed files with 13 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/gpu/drm/amd/display/dc/dc_types.h
View File

@ -261,6 +261,9 @@ struct dc_edid_caps {
bool edid_hdmi;
bool hdr_supported;
uint32_t max_tmds_clk_mhz;
uint32_t max_forum_tmds_clk_mhz;
struct dc_panel_patch panel_patch;
};

10
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
View File

@ -619,11 +619,20 @@ bool dcn10_link_encoder_validate_dvi_output(
static bool dcn10_link_encoder_validate_hdmi_output(
const struct dcn10_link_encoder *enc10,
const struct dc_crtc_timing *crtc_timing,
const struct dc_edid_caps *edid_caps,
int adjusted_pix_clk_100hz)
{
enum dc_color_depth max_deep_color =
enc10->base.features.max_hdmi_deep_color;
// check pixel clock against edid specified max TMDS clk
if (edid_caps->max_tmds_clk_mhz != 0 &&
adjusted_pix_clk_100hz > edid_caps->max_tmds_clk_mhz * 10000)
return false;
if (edid_caps->max_forum_tmds_clk_mhz != 0 &&
adjusted_pix_clk_100hz > edid_caps->max_forum_tmds_clk_mhz * 10000)
return false;
if (max_deep_color < crtc_timing->display_color_depth)
return false;
@ -801,6 +810,7 @@ bool dcn10_link_encoder_validate_output_with_stream(
is_valid = dcn10_link_encoder_validate_hdmi_output(
enc10,
&stream->timing,
&stream->sink->edid_caps,
stream->phy_pix_clk * 10);
break;
case SIGNAL_TYPE_DISPLAY_PORT: