PCI: pciehp: change wait time for valid configuration access
Naoki Yanagimoto reported that configuration read on some hot-added PCIe device returns invalid value. This patch fixes this problem. According to the PCIe spec, software must wait for at least 1 second to judge if the hot-added device is broken after Data Link Layer State Changed Event. This patch changes pciehp driver to wait for 1 second after the Data Link Layer State Changed Event is detected before initiating a configuration access instead of 100 ms. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Tested-by: Naoki Yanagimoto <yanagimoto@np.css.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
parent
9b373ed18f
commit
0cab0841dc
|
@ -213,6 +213,9 @@ static int board_added(struct slot *p_slot)
|
|||
goto err_exit;
|
||||
}
|
||||
|
||||
/* Wait for 1 second after checking link training status */
|
||||
msleep(1000);
|
||||
|
||||
/* Check for a power fault */
|
||||
if (ctrl->power_fault_detected || pciehp_query_power_fault(p_slot)) {
|
||||
ctrl_err(ctrl, "Power fault on slot %s\n", slot_name(p_slot));
|
||||
|
|
|
@ -275,16 +275,9 @@ int pciehp_check_link_status(struct controller *ctrl)
|
|||
* hot-plug capable downstream port. But old controller might
|
||||
* not implement it. In this case, we wait for 1000 ms.
|
||||
*/
|
||||
if (ctrl->link_active_reporting){
|
||||
/* Wait for Data Link Layer Link Active bit to be set */
|
||||
if (ctrl->link_active_reporting)
|
||||
pcie_wait_link_active(ctrl);
|
||||
/*
|
||||
* We must wait for 100 ms after the Data Link Layer
|
||||
* Link Active bit reads 1b before initiating a
|
||||
* configuration access to the hot added device.
|
||||
*/
|
||||
msleep(100);
|
||||
} else
|
||||
else
|
||||
msleep(1000);
|
||||
|
||||
retval = pciehp_readw(ctrl, PCI_EXP_LNKSTA, &lnk_status);
|
||||
|
|
Loading…
Reference in New Issue