usb: cdns2: Device side header file for CDNS2 driver
Patch defines macros, registers and structures used by Device side driver. Signed-off-by: Pawel Laszczak <pawell@cadence.com> Message-ID: <20230602102644.77470-2-pawell@cadence.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Pawel Laszczak
Greg Kroah-Hartman
parent
01052b91c9
commit
0ca2026eea
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* USBHS-DEV device controller driver header file
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*
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* Copyright (C) 2023 Cadence.
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*
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* Author: Pawel Laszczak <pawell@cadence.com>
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*/
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#ifndef __LINUX_CDNS2_GADGET
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#define __LINUX_CDNS2_GADGET
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#include <linux/usb/gadget.h>
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#include <linux/dma-direction.h>
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/*
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* USBHS register interface.
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* This corresponds to the USBHS Device Controller Interface.
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*/
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/**
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* struct cdns2_ep0_regs - endpoint 0 related registers.
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* @rxbc: receive (OUT) 0 endpoint byte count register.
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* @txbc: transmit (IN) 0 endpoint byte count register.
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* @cs: 0 endpoint control and status register.
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* @reserved1: reserved.
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* @fifo: 0 endpoint fifo register.
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* @reserved2: reserved.
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* @setupdat: SETUP data register.
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* @reserved4: reserved.
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* @maxpack: 0 endpoint max packet size.
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*/
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struct cdns2_ep0_regs {
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__u8 rxbc;
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__u8 txbc;
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__u8 cs;
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__u8 reserved1[4];
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__u8 fifo;
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__le32 reserved2[94];
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__u8 setupdat[8];
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__u8 reserved4[88];
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__u8 maxpack;
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} __packed __aligned(4);
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/* EP0CS - bitmasks. */
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/* Endpoint 0 stall bit for status stage. */
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#define EP0CS_STALL BIT(0)
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/* HSNAK bit. */
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#define EP0CS_HSNAK BIT(1)
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/* IN 0 endpoint busy bit. */
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#define EP0CS_TXBSY_MSK BIT(2)
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/* OUT 0 endpoint busy bit. */
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#define EP0CS_RXBSY_MSK BIT(3)
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/* Send STALL in the data stage phase. */
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#define EP0CS_DSTALL BIT(4)
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/* SETUP buffer content was changed. */
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#define EP0CS_CHGSET BIT(7)
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/* EP0FIFO - bitmasks. */
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/* Direction. */
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#define EP0_FIFO_IO_TX BIT(4)
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/* FIFO auto bit. */
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#define EP0_FIFO_AUTO BIT(5)
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/* FIFO commit bit. */
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#define EP0_FIFO_COMMIT BIT(6)
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/* FIFO access bit. */
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#define EP0_FIFO_ACCES BIT(7)
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/**
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* struct cdns2_epx_base - base endpoint registers.
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* @rxbc: OUT endpoint byte count register.
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* @rxcon: OUT endpoint control register.
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* @rxcs: OUT endpoint control and status register.
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* @txbc: IN endpoint byte count register.
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* @txcon: IN endpoint control register.
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* @txcs: IN endpoint control and status register.
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*/
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struct cdns2_epx_base {
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__le16 rxbc;
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__u8 rxcon;
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__u8 rxcs;
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__le16 txbc;
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__u8 txcon;
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__u8 txcs;
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} __packed __aligned(4);
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/* rxcon/txcon - endpoint control register bitmasks. */
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/* Endpoint buffering: 0 - single buffering ... 3 - quad buffering. */
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#define EPX_CON_BUF GENMASK(1, 0)
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/* Endpoint type. */
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#define EPX_CON_TYPE GENMASK(3, 2)
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/* Endpoint type: isochronous. */
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#define EPX_CON_TYPE_ISOC 0x4
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/* Endpoint type: bulk. */
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#define EPX_CON_TYPE_BULK 0x8
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/* Endpoint type: interrupt. */
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#define EPX_CON_TYPE_INT 0xC
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/* Number of packets per microframe. */
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#define EPX_CON_ISOD GENMASK(5, 4)
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#define EPX_CON_ISOD_SHIFT 0x4
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/* Endpoint stall bit. */
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#define EPX_CON_STALL BIT(6)
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/* Endpoint enable bit.*/
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#define EPX_CON_VAL BIT(7)
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/* rxcs/txcs - endpoint control and status bitmasks. */
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/* Data sequence error for the ISO endpoint. */
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#define EPX_CS_ERR(p) ((p) & BIT(0))
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/**
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* struct cdns2_epx_regs - endpoint 1..15 related registers.
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* @reserved: reserved.
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* @ep: none control endpoints array.
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* @reserved2: reserved.
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* @endprst: endpoint reset register.
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* @reserved3: reserved.
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* @isoautoarm: ISO auto-arm register.
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* @reserved4: reserved.
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* @isodctrl: ISO control register.
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* @reserved5: reserved.
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* @isoautodump: ISO auto dump enable register.
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* @reserved6: reserved.
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* @rxmaxpack: receive (OUT) Max packet size register.
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* @reserved7: reserved.
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* @rxstaddr: receive (OUT) start address endpoint buffer register.
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* @reserved8: reserved.
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* @txstaddr: transmit (IN) start address endpoint buffer register.
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* @reserved9: reserved.
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* @txmaxpack: transmit (IN) Max packet size register.
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*/
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struct cdns2_epx_regs {
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__le32 reserved[2];
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struct cdns2_epx_base ep[15];
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__u8 reserved2[290];
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__u8 endprst;
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__u8 reserved3[41];
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__le16 isoautoarm;
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__u8 reserved4[10];
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__le16 isodctrl;
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__le16 reserved5;
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__le16 isoautodump;
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__le32 reserved6;
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__le16 rxmaxpack[15];
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__le32 reserved7[65];
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__le32 rxstaddr[15];
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__u8 reserved8[4];
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__le32 txstaddr[15];
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__u8 reserved9[98];
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__le16 txmaxpack[15];
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} __packed __aligned(4);
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/* ENDPRST - bitmasks. */
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/* Endpoint number. */
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#define ENDPRST_EP GENMASK(3, 0)
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/* IN direction bit. */
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#define ENDPRST_IO_TX BIT(4)
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/* Toggle reset bit. */
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#define ENDPRST_TOGRST BIT(5)
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/* FIFO reset bit. */
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#define ENDPRST_FIFORST BIT(6)
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/* Toggle status and reset bit. */
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#define ENDPRST_TOGSETQ BIT(7)
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/**
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* struct cdns2_interrupt_regs - USB interrupt related registers.
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* @reserved: reserved.
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* @usbirq: USB interrupt request register.
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* @extirq: external interrupt request register.
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* @rxpngirq: external interrupt request register.
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* @reserved1: reserved.
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* @usbien: USB interrupt enable register.
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* @extien: external interrupt enable register.
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* @reserved2: reserved.
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* @usbivect: USB interrupt vector register.
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*/
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struct cdns2_interrupt_regs {
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__u8 reserved[396];
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__u8 usbirq;
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__u8 extirq;
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__le16 rxpngirq;
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__le16 reserved1[4];
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__u8 usbien;
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__u8 extien;
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__le16 reserved2[3];
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__u8 usbivect;
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} __packed __aligned(4);
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/* EXTIRQ and EXTIEN - bitmasks. */
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/* VBUS fault fall interrupt. */
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#define EXTIRQ_VBUSFAULT_FALL BIT(0)
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/* VBUS fault fall interrupt. */
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#define EXTIRQ_VBUSFAULT_RISE BIT(1)
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/* Wake up interrupt bit. */
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#define EXTIRQ_WAKEUP BIT(7)
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/* USBIEN and USBIRQ - bitmasks. */
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/* SETUP data valid interrupt bit.*/
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#define USBIRQ_SUDAV BIT(0)
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/* Start-of-frame interrupt bit. */
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#define USBIRQ_SOF BIT(1)
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/* SETUP token interrupt bit. */
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#define USBIRQ_SUTOK BIT(2)
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/* USB suspend interrupt bit. */
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#define USBIRQ_SUSPEND BIT(3)
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/* USB reset interrupt bit. */
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#define USBIRQ_URESET BIT(4)
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/* USB high-speed mode interrupt bit. */
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#define USBIRQ_HSPEED BIT(5)
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/* Link Power Management interrupt bit. */
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#define USBIRQ_LPM BIT(7)
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#define USB_IEN_INIT (USBIRQ_SUDAV | USBIRQ_SUSPEND | USBIRQ_URESET \
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| USBIRQ_HSPEED | USBIRQ_LPM)
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/**
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* struct cdns2_usb_regs - USB controller registers.
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* @reserved: reserved.
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* @lpmctrl: LPM control register.
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* @lpmclock: LPM clock register.
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* @reserved2: reserved.
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* @endprst: endpoint reset register.
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* @usbcs: USB control and status register.
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* @frmnr: USB frame counter register.
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* @fnaddr: function Address register.
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* @clkgate: clock gate register.
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* @fifoctrl: FIFO control register.
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* @speedctrl: speed Control register.
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* @sleep_clkgate: sleep Clock Gate register.
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* @reserved3: reserved.
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* @cpuctrl: microprocessor control register.
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*/
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struct cdns2_usb_regs {
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__u8 reserved[4];
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__u16 lpmctrl;
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__u8 lpmclock;
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__u8 reserved2[411];
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__u8 endprst;
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__u8 usbcs;
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__le16 frmnr;
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__u8 fnaddr;
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__u8 clkgate;
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__u8 fifoctrl;
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__u8 speedctrl;
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__u8 sleep_clkgate;
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__u8 reserved3[533];
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__u8 cpuctrl;
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} __packed __aligned(4);
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/* LPMCTRL - bitmasks. */
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/* BESL (Best Effort Service Latency). */
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#define LPMCTRLLL_HIRD GENMASK(7, 4)
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/* Last received Remote Wakeup field from LPM Extended Token packet. */
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#define LPMCTRLLH_BREMOTEWAKEUP BIT(8)
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/* Reflects value of the lpmnyet bit located in the usbcs[1] register. */
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#define LPMCTRLLH_LPMNYET BIT(16)
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/* LPMCLOCK - bitmasks. */
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/*
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* If bit is 1 the controller automatically turns off clock
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* (utmisleepm goes to low), else the microprocessor should use
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* sleep clock gate register to turn off clock.
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*/
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#define LPMCLOCK_SLEEP_ENTRY BIT(7)
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/* USBCS - bitmasks. */
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/* Send NYET handshake for the LPM transaction. */
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#define USBCS_LPMNYET BIT(2)
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/* Remote wake-up bit. */
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#define USBCS_SIGRSUME BIT(5)
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/* Software disconnect bit. */
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#define USBCS_DISCON BIT(6)
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/* Indicates that a wakeup pin resumed the controller. */
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#define USBCS_WAKESRC BIT(7)
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/* FIFOCTRL - bitmasks. */
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/* Endpoint number. */
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#define FIFOCTRL_EP GENMASK(3, 0)
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/* Direction bit. */
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#define FIFOCTRL_IO_TX BIT(4)
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/* FIFO auto bit. */
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#define FIFOCTRL_FIFOAUTO BIT(5)
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/* FIFO commit bit. */
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#define FIFOCTRL_FIFOCMIT BIT(6)
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/* FIFO access bit. */
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#define FIFOCTRL_FIFOACC BIT(7)
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/* SPEEDCTRL - bitmasks. */
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/* Device works in Full Speed. */
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#define SPEEDCTRL_FS BIT(1)
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/* Device works in High Speed. */
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#define SPEEDCTRL_HS BIT(2)
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/* Force FS mode. */
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#define SPEEDCTRL_HSDISABLE BIT(7)
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/* CPUCTRL- bitmasks. */
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/* Controller reset bit. */
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#define CPUCTRL_SW_RST BIT(1)
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/**
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* struct cdns2_adma_regs - ADMA controller registers.
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* @conf: DMA global configuration register.
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* @sts: DMA global Status register.
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* @reserved1: reserved.
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* @ep_sel: DMA endpoint select register.
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* @ep_traddr: DMA endpoint transfer ring address register.
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* @ep_cfg: DMA endpoint configuration register.
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* @ep_cmd: DMA endpoint command register.
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* @ep_sts: DMA endpoint status register.
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* @reserved2: reserved.
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* @ep_sts_en: DMA endpoint status enable register.
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* @drbl: DMA doorbell register.
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* @ep_ien: DMA endpoint interrupt enable register.
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* @ep_ists: DMA endpoint interrupt status register.
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* @axim_ctrl: AXI Master Control register.
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* @axim_id: AXI Master ID register.
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* @reserved3: reserved.
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* @axim_cap: AXI Master Wrapper Extended Capability.
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* @reserved4: reserved.
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* @axim_ctrl0: AXI Master Wrapper Extended Capability Control Register 0.
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* @axim_ctrl1: AXI Master Wrapper Extended Capability Control Register 1.
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*/
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struct cdns2_adma_regs {
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__le32 conf;
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__le32 sts;
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__le32 reserved1[5];
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__le32 ep_sel;
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__le32 ep_traddr;
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__le32 ep_cfg;
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__le32 ep_cmd;
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__le32 ep_sts;
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__le32 reserved2;
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__le32 ep_sts_en;
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__le32 drbl;
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__le32 ep_ien;
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__le32 ep_ists;
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__le32 axim_ctrl;
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__le32 axim_id;
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__le32 reserved3;
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__le32 axim_cap;
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__le32 reserved4;
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__le32 axim_ctrl0;
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__le32 axim_ctrl1;
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};
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#define CDNS2_ADMA_REGS_OFFSET 0x400
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/* DMA_CONF - bitmasks. */
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/* Reset USB device configuration. */
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#define DMA_CONF_CFGRST BIT(0)
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/* Singular DMA transfer mode.*/
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#define DMA_CONF_DSING BIT(8)
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/* Multiple DMA transfers mode.*/
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#define DMA_CONF_DMULT BIT(9)
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/* DMA_EP_CFG - bitmasks. */
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/* Endpoint enable. */
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#define DMA_EP_CFG_ENABLE BIT(0)
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/* DMA_EP_CMD - bitmasks. */
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/* Endpoint reset. */
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#define DMA_EP_CMD_EPRST BIT(0)
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/* Transfer descriptor ready. */
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#define DMA_EP_CMD_DRDY BIT(6)
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/* Data flush. */
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#define DMA_EP_CMD_DFLUSH BIT(7)
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/* DMA_EP_STS - bitmasks. */
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/* Interrupt On Complete. */
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#define DMA_EP_STS_IOC BIT(2)
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/* Interrupt on Short Packet. */
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#define DMA_EP_STS_ISP BIT(3)
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/* Transfer descriptor missing. */
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#define DMA_EP_STS_DESCMIS BIT(4)
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/* TRB error. */
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#define DMA_EP_STS_TRBERR BIT(7)
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/* DMA busy bit. */
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#define DMA_EP_STS_DBUSY BIT(9)
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/* Current Cycle Status. */
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#define DMA_EP_STS_CCS(p) ((p) & BIT(11))
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/* OUT size mismatch. */
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#define DMA_EP_STS_OUTSMM BIT(14)
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/* ISO transmission error. */
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#define DMA_EP_STS_ISOERR BIT(15)
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/* DMA_EP_STS_EN - bitmasks. */
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/* OUT transfer missing descriptor enable. */
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#define DMA_EP_STS_EN_DESCMISEN BIT(4)
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/* TRB enable. */
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#define DMA_EP_STS_EN_TRBERREN BIT(7)
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/* OUT size mismatch enable. */
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#define DMA_EP_STS_EN_OUTSMMEN BIT(14)
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/* ISO transmission error enable. */
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#define DMA_EP_STS_EN_ISOERREN BIT(15)
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/* DMA_EP_IEN - bitmasks. */
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#define DMA_EP_IEN(index) (1 << (index))
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#define DMA_EP_IEN_EP_OUT0 BIT(0)
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#define DMA_EP_IEN_EP_IN0 BIT(16)
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/* DMA_EP_ISTS - bitmasks. */
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#define DMA_EP_ISTS(index) (1 << (index))
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#define DMA_EP_ISTS_EP_OUT0 BIT(0)
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#define DMA_EP_ISTS_EP_IN0 BIT(16)
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#define gadget_to_cdns2_device(g) (container_of(g, struct cdns2_device, gadget))
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#define ep_to_cdns2_ep(ep) (container_of(ep, struct cdns2_endpoint, endpoint))
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/*-------------------------------------------------------------------------*/
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#define TRBS_PER_SEGMENT 600
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#define ISO_MAX_INTERVAL 8
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#define MAX_TRB_LENGTH BIT(16)
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#define MAX_ISO_SIZE 3076
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/*
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* To improve performance the TRB buffer pointers can't cross
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* 4KB boundaries.
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*/
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#define TRB_MAX_ISO_BUFF_SHIFT 12
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#define TRB_MAX_ISO_BUFF_SIZE BIT(TRB_MAX_ISO_BUFF_SHIFT)
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/* How much data is left before the 4KB boundary? */
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#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_ISO_BUFF_SIZE - \
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((addr) & (TRB_MAX_ISO_BUFF_SIZE - 1)))
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#if TRBS_PER_SEGMENT < 2
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#error "Incorrect TRBS_PER_SEGMENT. Minimal Transfer Ring size is 2."
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#endif
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/**
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* struct cdns2_trb - represent Transfer Descriptor block.
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* @buffer: pointer to buffer data.
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* @length: length of data.
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* @control: control flags.
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*
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* This structure describes transfer block handled by DMA module.
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*/
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struct cdns2_trb {
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__le32 buffer;
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__le32 length;
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__le32 control;
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};
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#define TRB_SIZE (sizeof(struct cdns2_trb))
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/*
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* These two extra TRBs are reserved for isochronous transfer
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* to inject 0 length packet and extra LINK TRB to synchronize the ISO transfer.
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*/
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#define TRB_ISO_RESERVED 2
|
||||
#define TR_SEG_SIZE (TRB_SIZE * (TRBS_PER_SEGMENT + TRB_ISO_RESERVED))
|
||||
|
||||
/* TRB bit mask. */
|
||||
#define TRB_TYPE_BITMASK GENMASK(15, 10)
|
||||
#define TRB_TYPE(p) ((p) << 10)
|
||||
#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
|
||||
|
||||
/* TRB type IDs. */
|
||||
/* Used for Bulk, Interrupt, ISOC, and control data stage. */
|
||||
#define TRB_NORMAL 1
|
||||
/* TRB for linking ring segments. */
|
||||
#define TRB_LINK 6
|
||||
|
||||
/* Cycle bit - indicates TRB ownership by driver or hw. */
|
||||
#define TRB_CYCLE BIT(0)
|
||||
/*
|
||||
* When set to '1', the device will toggle its interpretation of the Cycle bit.
|
||||
*/
|
||||
#define TRB_TOGGLE BIT(1)
|
||||
/* Interrupt on short packet. */
|
||||
#define TRB_ISP BIT(2)
|
||||
/* Chain bit associate this TRB with next one TRB. */
|
||||
#define TRB_CHAIN BIT(4)
|
||||
/* Interrupt on completion. */
|
||||
#define TRB_IOC BIT(5)
|
||||
|
||||
/* Transfer_len bitmasks. */
|
||||
#define TRB_LEN(p) ((p) & GENMASK(16, 0))
|
||||
#define TRB_BURST(p) (((p) << 24) & GENMASK(31, 24))
|
||||
#define TRB_FIELD_TO_BURST(p) (((p) & GENMASK(31, 24)) >> 24)
|
||||
|
||||
/* Data buffer pointer bitmasks. */
|
||||
#define TRB_BUFFER(p) ((p) & GENMASK(31, 0))
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
/* Driver numeric constants. */
|
||||
|
||||
/* Maximum address that can be assigned to device. */
|
||||
#define USB_DEVICE_MAX_ADDRESS 127
|
||||
|
||||
/* One control and 15 IN and 15 OUT endpoints. */
|
||||
#define CDNS2_ENDPOINTS_NUM 31
|
||||
|
||||
#define CDNS2_EP_ZLP_BUF_SIZE 512
|
||||
|
||||
/*-------------------------------------------------------------------------*/
|
||||
/* Used structures. */
|
||||
|
||||
struct cdns2_device;
|
||||
|
||||
/**
|
||||
* struct cdns2_ring - transfer ring representation.
|
||||
* @trbs: pointer to transfer ring.
|
||||
* @dma: dma address of transfer ring.
|
||||
* @free_trbs: number of free TRBs in transfer ring.
|
||||
* @pcs: producer cycle state.
|
||||
* @ccs: consumer cycle state.
|
||||
* @enqueue: enqueue index in transfer ring.
|
||||
* @dequeue: dequeue index in transfer ring.
|
||||
*/
|
||||
struct cdns2_ring {
|
||||
struct cdns2_trb *trbs;
|
||||
dma_addr_t dma;
|
||||
int free_trbs;
|
||||
u8 pcs;
|
||||
u8 ccs;
|
||||
int enqueue;
|
||||
int dequeue;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct cdns2_endpoint - extended device side representation of USB endpoint.
|
||||
* @endpoint: usb endpoint.
|
||||
* @pending_list: list of requests queuing on transfer ring.
|
||||
* @deferred_list: list of requests waiting for queuing on transfer ring.
|
||||
* @pdev: device associated with endpoint.
|
||||
* @name: a human readable name e.g. ep1out.
|
||||
* @ring: transfer ring associated with endpoint.
|
||||
* @ep_state: state of endpoint.
|
||||
* @idx: index of endpoint in pdev->eps table.
|
||||
* @dir: endpoint direction.
|
||||
* @num: endpoint number (1 - 15).
|
||||
* @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK.
|
||||
* @interval: interval between packets used for ISOC and Interrupt endpoint.
|
||||
* @buffering: on-chip buffers assigned to endpoint.
|
||||
* @trb_burst_size: number of burst used in TRB.
|
||||
* @skip: Sometimes the controller cannot process isochronous endpoint ring
|
||||
* quickly enough and it will miss some isoc tds on the ring and
|
||||
* generate ISO transmition error.
|
||||
* Driver sets skip flag when receive a ISO transmition error and
|
||||
* process the missed TDs on the endpoint ring.
|
||||
* @wa1_set: use WA1.
|
||||
* @wa1_trb: TRB assigned to WA1.
|
||||
* @wa1_trb_index: TRB index for WA1.
|
||||
* @wa1_cycle_bit: correct cycle bit for WA1.
|
||||
*/
|
||||
struct cdns2_endpoint {
|
||||
struct usb_ep endpoint;
|
||||
struct list_head pending_list;
|
||||
struct list_head deferred_list;
|
||||
|
||||
struct cdns2_device *pdev;
|
||||
char name[20];
|
||||
|
||||
struct cdns2_ring ring;
|
||||
|
||||
#define EP_ENABLED BIT(0)
|
||||
#define EP_STALLED BIT(1)
|
||||
#define EP_STALL_PENDING BIT(2)
|
||||
#define EP_WEDGE BIT(3)
|
||||
#define EP_CLAIMED BIT(4)
|
||||
#define EP_RING_FULL BIT(5)
|
||||
#define EP_DEFERRED_DRDY BIT(6)
|
||||
|
||||
u32 ep_state;
|
||||
|
||||
u8 idx;
|
||||
u8 dir;
|
||||
u8 num;
|
||||
u8 type;
|
||||
int interval;
|
||||
u8 buffering;
|
||||
u8 trb_burst_size;
|
||||
bool skip;
|
||||
|
||||
unsigned int wa1_set:1;
|
||||
struct cdns2_trb *wa1_trb;
|
||||
unsigned int wa1_trb_index;
|
||||
unsigned int wa1_cycle_bit:1;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct cdns2_request - extended device side representation of usb_request
|
||||
* object.
|
||||
* @request: generic usb_request object describing single I/O request.
|
||||
* @pep: extended representation of usb_ep object.
|
||||
* @trb: the first TRB association with this request.
|
||||
* @start_trb: number of the first TRB in transfer ring.
|
||||
* @end_trb: number of the last TRB in transfer ring.
|
||||
* @list: used for queuing request in lists.
|
||||
* @finished_trb: number of trb has already finished per request.
|
||||
* @num_of_trb: how many trbs are associated with request.
|
||||
*/
|
||||
struct cdns2_request {
|
||||
struct usb_request request;
|
||||
struct cdns2_endpoint *pep;
|
||||
struct cdns2_trb *trb;
|
||||
int start_trb;
|
||||
int end_trb;
|
||||
struct list_head list;
|
||||
int finished_trb;
|
||||
int num_of_trb;
|
||||
};
|
||||
|
||||
#define to_cdns2_request(r) (container_of(r, struct cdns2_request, request))
|
||||
|
||||
/* Stages used during enumeration process.*/
|
||||
#define CDNS2_SETUP_STAGE 0x0
|
||||
#define CDNS2_DATA_STAGE 0x1
|
||||
#define CDNS2_STATUS_STAGE 0x2
|
||||
|
||||
/**
|
||||
* struct cdns2_device - represent USB device.
|
||||
* @dev: pointer to device structure associated whit this controller.
|
||||
* @gadget: device side representation of the peripheral controller.
|
||||
* @gadget_driver: pointer to the gadget driver.
|
||||
* @lock: for synchronizing.
|
||||
* @irq: interrupt line number.
|
||||
* @regs: base address for registers
|
||||
* @usb_regs: base address for common USB registers.
|
||||
* @ep0_regs: base address for endpoint 0 related registers.
|
||||
* @epx_regs: base address for all none control endpoint registers.
|
||||
* @interrupt_regs: base address for interrupt handling related registers.
|
||||
* @adma_regs: base address for ADMA registers.
|
||||
* @eps_dma_pool: endpoint Transfer Ring pool.
|
||||
* @setup: used while processing usb control requests.
|
||||
* @ep0_preq: private request used while handling EP0.
|
||||
* @ep0_stage: ep0 stage during enumeration process.
|
||||
* @zlp_buf: zlp buffer.
|
||||
* @dev_address: device address assigned by host.
|
||||
* @eps: array of objects describing endpoints.
|
||||
* @selected_ep: actually selected endpoint. It's used only to improve
|
||||
* performance by limiting access to dma_ep_sel register.
|
||||
* @is_selfpowered: device is self powered.
|
||||
* @may_wakeup: allows device to remote wakeup the host.
|
||||
* @status_completion_no_call: indicate that driver is waiting for status
|
||||
* stage completion. It's used in deferred SET_CONFIGURATION request.
|
||||
* @in_lpm: indicate the controller is in low power mode.
|
||||
* @pending_status_wq: workqueue handling status stage for deferred requests.
|
||||
* @pending_status_request: request for which status stage was deferred.
|
||||
* @eps_supported: endpoints supported by controller in form:
|
||||
* bit: 0 - ep0, 1 - epOut1, 2 - epIn1, 3 - epOut2 ...
|
||||
* @burst_opt: array with the best burst size value for different TRB size.
|
||||
* @onchip_tx_buf: size of transmit on-chip buffer in KB.
|
||||
* @onchip_rx_buf: size of receive on-chip buffer in KB.
|
||||
*/
|
||||
struct cdns2_device {
|
||||
struct device *dev;
|
||||
struct usb_gadget gadget;
|
||||
struct usb_gadget_driver *gadget_driver;
|
||||
|
||||
/* generic spin-lock for drivers */
|
||||
spinlock_t lock;
|
||||
int irq;
|
||||
void __iomem *regs;
|
||||
struct cdns2_usb_regs __iomem *usb_regs;
|
||||
struct cdns2_ep0_regs __iomem *ep0_regs;
|
||||
struct cdns2_epx_regs __iomem *epx_regs;
|
||||
struct cdns2_interrupt_regs __iomem *interrupt_regs;
|
||||
struct cdns2_adma_regs __iomem *adma_regs;
|
||||
struct dma_pool *eps_dma_pool;
|
||||
struct usb_ctrlrequest setup;
|
||||
struct cdns2_request ep0_preq;
|
||||
u8 ep0_stage;
|
||||
void *zlp_buf;
|
||||
u8 dev_address;
|
||||
struct cdns2_endpoint eps[CDNS2_ENDPOINTS_NUM];
|
||||
u32 selected_ep;
|
||||
bool is_selfpowered;
|
||||
bool may_wakeup;
|
||||
bool status_completion_no_call;
|
||||
bool in_lpm;
|
||||
struct work_struct pending_status_wq;
|
||||
struct usb_request *pending_status_request;
|
||||
u32 eps_supported;
|
||||
u8 burst_opt[MAX_ISO_SIZE + 1];
|
||||
|
||||
/*in KB */
|
||||
u16 onchip_tx_buf;
|
||||
u16 onchip_rx_buf;
|
||||
};
|
||||
|
||||
#define CDNS2_IF_EP_EXIST(pdev, ep_num, dir) \
|
||||
((pdev)->eps_supported & \
|
||||
(BIT(ep_num) << ((dir) ? 0 : 16)))
|
||||
|
||||
dma_addr_t cdns2_trb_virt_to_dma(struct cdns2_endpoint *pep,
|
||||
struct cdns2_trb *trb);
|
||||
void cdns2_pending_setup_status_handler(struct work_struct *work);
|
||||
void cdns2_select_ep(struct cdns2_device *pdev, u32 ep);
|
||||
struct cdns2_request *cdns2_next_preq(struct list_head *list);
|
||||
struct usb_request *cdns2_gadget_ep_alloc_request(struct usb_ep *ep,
|
||||
gfp_t gfp_flags);
|
||||
void cdns2_gadget_ep_free_request(struct usb_ep *ep,
|
||||
struct usb_request *request);
|
||||
int cdns2_gadget_ep_dequeue(struct usb_ep *ep, struct usb_request *request);
|
||||
void cdns2_gadget_giveback(struct cdns2_endpoint *pep,
|
||||
struct cdns2_request *priv_req,
|
||||
int status);
|
||||
void cdns2_init_ep0(struct cdns2_device *pdev, struct cdns2_endpoint *pep);
|
||||
void cdns2_ep0_config(struct cdns2_device *pdev);
|
||||
void cdns2_handle_ep0_interrupt(struct cdns2_device *pdev, int dir);
|
||||
void cdns2_handle_setup_packet(struct cdns2_device *pdev);
|
||||
int cdns2_gadget_resume(struct cdns2_device *pdev, bool hibernated);
|
||||
int cdns2_gadget_suspend(struct cdns2_device *pdev);
|
||||
void cdns2_gadget_remove(struct cdns2_device *pdev);
|
||||
int cdns2_gadget_init(struct cdns2_device *pdev);
|
||||
void set_reg_bit_8(void __iomem *ptr, u8 mask);
|
||||
int cdns2_halt_endpoint(struct cdns2_device *pdev, struct cdns2_endpoint *pep,
|
||||
int value);
|
||||
|
||||
#endif /* __LINUX_CDNS2_GADGET */
|
||||
Loading…
Reference in New Issue