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drm/amd/display: Program v_total_min/max after v_total_cntl 

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Anthony Koo 2018-03-15 13:46:50 -04:00 committed by Alex Deucher
parent 5cd29ed0cb
commit 0c8df4bbc4
3 changed files with 20 additions and 20 deletions
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16
drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c
View File

@ -431,14 +431,6 @@ void dce110_timing_generator_set_drr(
0,
CRTC_V_TOTAL_CONTROL,
CRTC_SET_V_TOTAL_MIN_MASK);
set_reg_field_value(v_total_min,
0,
CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN);
set_reg_field_value(v_total_max,
0,
CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX);
set_reg_field_value(v_total_cntl,
0,
CRTC_V_TOTAL_CONTROL,
@ -447,6 +439,14 @@ void dce110_timing_generator_set_drr(
0,
CRTC_V_TOTAL_CONTROL,
CRTC_V_TOTAL_MAX_SEL);
set_reg_field_value(v_total_min,
0,
CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN);
set_reg_field_value(v_total_max,
0,
CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX);
set_reg_field_value(v_total_cntl,
0,
CRTC_V_TOTAL_CONTROL,

12
drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c
View File

@ -570,18 +570,18 @@ void dce120_timing_generator_set_drr(
0x180);
} else {
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN, 0);
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX, 0);
CRTC_REG_SET_N(CRTC0_CRTC_V_TOTAL_CONTROL, 5,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MIN_SEL), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_V_TOTAL_MAX_SEL), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_ON_EVENT), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_FORCE_LOCK_TO_MASTER_VSYNC), 0,
FD(CRTC0_CRTC_V_TOTAL_CONTROL__CRTC_SET_V_TOTAL_MIN_MASK), 0);
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MIN,
CRTC_V_TOTAL_MIN, 0);
CRTC_REG_UPDATE(
CRTC0_CRTC_V_TOTAL_MAX,
CRTC_V_TOTAL_MAX, 0);
CRTC_REG_UPDATE(
CRTC0_CRTC_STATIC_SCREEN_CONTROL,
CRTC_STATIC_SCREEN_EVENT_MASK,

12
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
View File

@ -855,17 +855,17 @@ void optc1_set_drr(
OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
OTG_SET_V_TOTAL_MIN_MASK, 0);
} else {
REG_SET(OTG_V_TOTAL_MIN, 0,
OTG_V_TOTAL_MIN, 0);
REG_SET(OTG_V_TOTAL_MAX, 0,
OTG_V_TOTAL_MAX, 0);
REG_UPDATE_4(OTG_V_TOTAL_CONTROL,
OTG_SET_V_TOTAL_MIN_MASK, 0,
OTG_V_TOTAL_MIN_SEL, 0,
OTG_V_TOTAL_MAX_SEL, 0,
OTG_FORCE_LOCK_ON_EVENT, 0);
REG_SET(OTG_V_TOTAL_MIN, 0,
OTG_V_TOTAL_MIN, 0);
REG_SET(OTG_V_TOTAL_MAX, 0,
OTG_V_TOTAL_MAX, 0);
}
}