mtd: fsl_ifc_nand: use more portable i/o accessors
in/out_be32 accessors are Power arch centric whereas ioread/writebe32 are available in other arches. Since the IFC device registers are annotated big endian in fsl_ifc.h, the accessor annotations now match, resulting in the pleasant side-effect of this patch silencing sparse endian warnings such as the following: drivers/mtd/nand/fsl_ifc_nand.c:179:19: warning: incorrect type in argument 1 (different base types) drivers/mtd/nand/fsl_ifc_nand.c:179:19: expected unsigned int volatile [noderef] [usertype] <asn:2>*addr drivers/mtd/nand/fsl_ifc_nand.c:179:19: got restricted __be32 [noderef] <asn:2>*<noident> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
This commit is contained in:
Kim Phillips
Artem Bityutskiy
parent
44fe63fc0f
commit
0c69fb037a
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@ -176,8 +176,8 @@ static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
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ifc_nand_ctrl->page = page_addr;
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/* Program ROW0/COL0 */
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out_be32(&ifc->ifc_nand.row0, page_addr);
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out_be32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
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iowrite32be(page_addr, &ifc->ifc_nand.row0);
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iowrite32be((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
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buf_num = page_addr & priv->bufnum_mask;
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@ -239,18 +239,19 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
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int i;
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/* set the chip select for NAND Transaction */
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out_be32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
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iowrite32be(priv->bank << IFC_NAND_CSEL_SHIFT,
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&ifc->ifc_nand.nand_csel);
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dev_vdbg(priv->dev,
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"%s: fir0=%08x fcr0=%08x\n",
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__func__,
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in_be32(&ifc->ifc_nand.nand_fir0),
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in_be32(&ifc->ifc_nand.nand_fcr0));
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ioread32be(&ifc->ifc_nand.nand_fir0),
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ioread32be(&ifc->ifc_nand.nand_fcr0));
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ctrl->nand_stat = 0;
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/* start read/write seq */
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out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
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iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
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/* wait for command complete flag or timeout */
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wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
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@ -273,7 +274,7 @@ static void fsl_ifc_run_command(struct mtd_info *mtd)
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int sector_end = sector + chip->ecc.steps - 1;
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for (i = sector / 4; i <= sector_end / 4; i++)
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eccstat[i] = in_be32(&ifc->ifc_nand.nand_eccstat[i]);
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eccstat[i] = ioread32be(&ifc->ifc_nand.nand_eccstat[i]);
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for (i = sector; i <= sector_end; i++) {
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errors = check_read_ecc(mtd, ctrl, eccstat, i);
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@ -313,31 +314,33 @@ static void fsl_ifc_do_read(struct nand_chip *chip,
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/* Program FIR/IFC_NAND_FCR0 for Small/Large page */
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if (mtd->writesize > 512) {
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
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(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
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(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
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&ifc->ifc_nand.nand_fir0);
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iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
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out_be32(&ifc->ifc_nand.nand_fcr0,
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(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
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(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
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iowrite32be((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
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(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
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&ifc->ifc_nand.nand_fcr0);
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} else {
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fir1, 0x0);
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(IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
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&ifc->ifc_nand.nand_fir0);
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iowrite32be(0x0, &ifc->ifc_nand.nand_fir1);
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if (oob)
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out_be32(&ifc->ifc_nand.nand_fcr0,
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NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
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iowrite32be(NAND_CMD_READOOB <<
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IFC_NAND_FCR0_CMD0_SHIFT,
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&ifc->ifc_nand.nand_fcr0);
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else
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out_be32(&ifc->ifc_nand.nand_fcr0,
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NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
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iowrite32be(NAND_CMD_READ0 <<
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IFC_NAND_FCR0_CMD0_SHIFT,
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&ifc->ifc_nand.nand_fcr0);
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}
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}
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@ -357,7 +360,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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switch (command) {
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/* READ0 read the entire buffer to use hardware ECC. */
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case NAND_CMD_READ0:
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out_be32(&ifc->ifc_nand.nand_fbcr, 0);
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iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
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set_addr(mtd, 0, page_addr, 0);
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ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
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@ -372,7 +375,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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/* READOOB reads only the OOB because no ECC is performed. */
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case NAND_CMD_READOOB:
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out_be32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
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iowrite32be(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
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set_addr(mtd, column, page_addr, 1);
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ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
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@ -388,19 +391,19 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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if (command == NAND_CMD_PARAM)
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timing = IFC_FIR_OP_RBCD;
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
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(timing << IFC_NAND_FIR0_OP2_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fcr0,
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command << IFC_NAND_FCR0_CMD0_SHIFT);
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out_be32(&ifc->ifc_nand.row3, column);
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(timing << IFC_NAND_FIR0_OP2_SHIFT),
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&ifc->ifc_nand.nand_fir0);
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iowrite32be(command << IFC_NAND_FCR0_CMD0_SHIFT,
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&ifc->ifc_nand.nand_fcr0);
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iowrite32be(column, &ifc->ifc_nand.row3);
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/*
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* although currently it's 8 bytes for READID, we always read
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* the maximum 256 bytes(for PARAM)
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*/
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out_be32(&ifc->ifc_nand.nand_fbcr, 256);
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iowrite32be(256, &ifc->ifc_nand.nand_fbcr);
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ifc_nand_ctrl->read_bytes = 256;
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set_addr(mtd, 0, 0, 0);
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@ -415,16 +418,16 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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/* ERASE2 uses the block and page address from ERASE1 */
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case NAND_CMD_ERASE2:
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
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(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
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&ifc->ifc_nand.nand_fir0);
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out_be32(&ifc->ifc_nand.nand_fcr0,
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(NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
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(NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
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iowrite32be((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
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(NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
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&ifc->ifc_nand.nand_fcr0);
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out_be32(&ifc->ifc_nand.nand_fbcr, 0);
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iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
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ifc_nand_ctrl->read_bytes = 0;
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fsl_ifc_run_command(mtd);
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return;
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@ -440,26 +443,28 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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(NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
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(NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD1_SHIFT);
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out_be32(&ifc->ifc_nand.nand_fir0,
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iowrite32be(
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
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(IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT));
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(IFC_FIR_OP_CW1 << IFC_NAND_FIR0_OP4_SHIFT),
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&ifc->ifc_nand.nand_fir0);
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} else {
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nand_fcr0 = ((NAND_CMD_PAGEPROG <<
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IFC_NAND_FCR0_CMD1_SHIFT) |
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(NAND_CMD_SEQIN <<
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IFC_NAND_FCR0_CMD2_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fir0,
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iowrite32be(
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
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(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fir1,
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(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT));
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(IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
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&ifc->ifc_nand.nand_fir0);
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iowrite32be(IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT,
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&ifc->ifc_nand.nand_fir1);
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if (column >= mtd->writesize)
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nand_fcr0 |=
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@ -474,7 +479,7 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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column -= mtd->writesize;
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ifc_nand_ctrl->oob = 1;
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}
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out_be32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
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iowrite32be(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
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set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
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return;
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}
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@ -482,10 +487,11 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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/* PAGEPROG reuses all of the setup from SEQIN and adds the length */
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case NAND_CMD_PAGEPROG: {
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if (ifc_nand_ctrl->oob) {
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out_be32(&ifc->ifc_nand.nand_fbcr,
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ifc_nand_ctrl->index - ifc_nand_ctrl->column);
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iowrite32be(ifc_nand_ctrl->index -
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ifc_nand_ctrl->column,
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&ifc->ifc_nand.nand_fbcr);
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} else {
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out_be32(&ifc->ifc_nand.nand_fbcr, 0);
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iowrite32be(0, &ifc->ifc_nand.nand_fbcr);
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}
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fsl_ifc_run_command(mtd);
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@ -493,12 +499,12 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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}
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case NAND_CMD_STATUS:
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fcr0,
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NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
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out_be32(&ifc->ifc_nand.nand_fbcr, 1);
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iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
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&ifc->ifc_nand.nand_fir0);
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iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
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&ifc->ifc_nand.nand_fcr0);
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iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
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set_addr(mtd, 0, 0, 0);
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ifc_nand_ctrl->read_bytes = 1;
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@ -512,10 +518,10 @@ static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
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return;
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case NAND_CMD_RESET:
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out_be32(&ifc->ifc_nand.nand_fir0,
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IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
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out_be32(&ifc->ifc_nand.nand_fcr0,
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NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
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iowrite32be(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
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&ifc->ifc_nand.nand_fir0);
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iowrite32be(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
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&ifc->ifc_nand.nand_fcr0);
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fsl_ifc_run_command(mtd);
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return;
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@ -639,18 +645,18 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
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u32 nand_fsr;
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/* Use READ_STATUS command, but wait for the device to be ready */
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out_be32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
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out_be32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
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IFC_NAND_FCR0_CMD0_SHIFT);
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out_be32(&ifc->ifc_nand.nand_fbcr, 1);
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iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
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&ifc->ifc_nand.nand_fir0);
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iowrite32be(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
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&ifc->ifc_nand.nand_fcr0);
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iowrite32be(1, &ifc->ifc_nand.nand_fbcr);
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set_addr(mtd, 0, 0, 0);
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ifc_nand_ctrl->read_bytes = 1;
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fsl_ifc_run_command(mtd);
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nand_fsr = in_be32(&ifc->ifc_nand.nand_fsr);
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nand_fsr = ioread32be(&ifc->ifc_nand.nand_fsr);
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/*
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* The chip always seems to report that it is
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@ -744,34 +750,34 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
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uint32_t cs = priv->bank;
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/* Save CSOR and CSOR_ext */
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csor = in_be32(&ifc->csor_cs[cs].csor);
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csor_ext = in_be32(&ifc->csor_cs[cs].csor_ext);
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csor = ioread32be(&ifc->csor_cs[cs].csor);
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csor_ext = ioread32be(&ifc->csor_cs[cs].csor_ext);
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/* chage PageSize 8K and SpareSize 1K*/
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csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
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out_be32(&ifc->csor_cs[cs].csor, csor_8k);
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out_be32(&ifc->csor_cs[cs].csor_ext, 0x0000400);
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iowrite32be(csor_8k, &ifc->csor_cs[cs].csor);
|
||||
iowrite32be(0x0000400, &ifc->csor_cs[cs].csor_ext);
|
||||
|
||||
/* READID */
|
||||
out_be32(&ifc->ifc_nand.nand_fir0,
|
||||
(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||
iowrite32be((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
|
||||
(IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
|
||||
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
|
||||
out_be32(&ifc->ifc_nand.nand_fcr0,
|
||||
NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
|
||||
out_be32(&ifc->ifc_nand.row3, 0x0);
|
||||
(IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
|
||||
&ifc->ifc_nand.nand_fir0);
|
||||
iowrite32be(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
|
||||
&ifc->ifc_nand.nand_fcr0);
|
||||
iowrite32be(0x0, &ifc->ifc_nand.row3);
|
||||
|
||||
out_be32(&ifc->ifc_nand.nand_fbcr, 0x0);
|
||||
iowrite32be(0x0, &ifc->ifc_nand.nand_fbcr);
|
||||
|
||||
/* Program ROW0/COL0 */
|
||||
out_be32(&ifc->ifc_nand.row0, 0x0);
|
||||
out_be32(&ifc->ifc_nand.col0, 0x0);
|
||||
iowrite32be(0x0, &ifc->ifc_nand.row0);
|
||||
iowrite32be(0x0, &ifc->ifc_nand.col0);
|
||||
|
||||
/* set the chip select for NAND Transaction */
|
||||
out_be32(&ifc->ifc_nand.nand_csel, cs << IFC_NAND_CSEL_SHIFT);
|
||||
iowrite32be(cs << IFC_NAND_CSEL_SHIFT, &ifc->ifc_nand.nand_csel);
|
||||
|
||||
/* start read seq */
|
||||
out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
|
||||
iowrite32be(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
|
||||
|
||||
/* wait for command complete flag or timeout */
|
||||
wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
|
||||
|
|
@ -781,8 +787,8 @@ static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
|
|||
printk(KERN_ERR "fsl-ifc: Failed to Initialise SRAM\n");
|
||||
|
||||
/* Restore CSOR and CSOR_ext */
|
||||
out_be32(&ifc->csor_cs[cs].csor, csor);
|
||||
out_be32(&ifc->csor_cs[cs].csor_ext, csor_ext);
|
||||
iowrite32be(csor, &ifc->csor_cs[cs].csor);
|
||||
iowrite32be(csor_ext, &ifc->csor_cs[cs].csor_ext);
|
||||
}
|
||||
|
||||
static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
|
||||
|
|
@ -799,7 +805,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
|
|||
|
||||
/* fill in nand_chip structure */
|
||||
/* set up function call table */
|
||||
if ((in_be32(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
|
||||
if ((ioread32be(&ifc->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
|
||||
chip->read_byte = fsl_ifc_read_byte16;
|
||||
else
|
||||
chip->read_byte = fsl_ifc_read_byte;
|
||||
|
|
@ -813,13 +819,13 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
|
|||
chip->bbt_td = &bbt_main_descr;
|
||||
chip->bbt_md = &bbt_mirror_descr;
|
||||
|
||||
out_be32(&ifc->ifc_nand.ncfgr, 0x0);
|
||||
iowrite32be(0x0, &ifc->ifc_nand.ncfgr);
|
||||
|
||||
/* set up nand options */
|
||||
chip->bbt_options = NAND_BBT_USE_FLASH;
|
||||
|
||||
|
||||
if (in_be32(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
|
||||
if (ioread32be(&ifc->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
|
||||
chip->read_byte = fsl_ifc_read_byte16;
|
||||
chip->options |= NAND_BUSWIDTH_16;
|
||||
} else {
|
||||
|
|
@ -832,7 +838,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
|
|||
chip->ecc.read_page = fsl_ifc_read_page;
|
||||
chip->ecc.write_page = fsl_ifc_write_page;
|
||||
|
||||
csor = in_be32(&ifc->csor_cs[priv->bank].csor);
|
||||
csor = ioread32be(&ifc->csor_cs[priv->bank].csor);
|
||||
|
||||
/* Hardware generates ECC per 512 Bytes */
|
||||
chip->ecc.size = 512;
|
||||
|
|
@ -884,7 +890,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
|
|||
chip->ecc.mode = NAND_ECC_SOFT;
|
||||
}
|
||||
|
||||
ver = in_be32(&ifc->ifc_rev);
|
||||
ver = ioread32be(&ifc->ifc_rev);
|
||||
if (ver == FSL_IFC_V1_1_0)
|
||||
fsl_ifc_sram_init(priv);
|
||||
|
||||
|
|
@ -910,7 +916,7 @@ static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
|
|||
static int match_bank(struct fsl_ifc_regs __iomem *ifc, int bank,
|
||||
phys_addr_t addr)
|
||||
{
|
||||
u32 cspr = in_be32(&ifc->cspr_cs[bank].cspr);
|
||||
u32 cspr = ioread32be(&ifc->cspr_cs[bank].cspr);
|
||||
|
||||
if (!(cspr & CSPR_V))
|
||||
return 0;
|
||||
|
|
@ -997,17 +1003,16 @@ static int fsl_ifc_nand_probe(struct platform_device *dev)
|
|||
|
||||
dev_set_drvdata(priv->dev, priv);
|
||||
|
||||
out_be32(&ifc->ifc_nand.nand_evter_en,
|
||||
IFC_NAND_EVTER_EN_OPC_EN |
|
||||
iowrite32be(IFC_NAND_EVTER_EN_OPC_EN |
|
||||
IFC_NAND_EVTER_EN_FTOER_EN |
|
||||
IFC_NAND_EVTER_EN_WPER_EN);
|
||||
IFC_NAND_EVTER_EN_WPER_EN,
|
||||
&ifc->ifc_nand.nand_evter_en);
|
||||
|
||||
/* enable NAND Machine Interrupts */
|
||||
out_be32(&ifc->ifc_nand.nand_evter_intr_en,
|
||||
IFC_NAND_EVTER_INTR_OPCIR_EN |
|
||||
iowrite32be(IFC_NAND_EVTER_INTR_OPCIR_EN |
|
||||
IFC_NAND_EVTER_INTR_FTOERIR_EN |
|
||||
IFC_NAND_EVTER_INTR_WPERIR_EN);
|
||||
|
||||
IFC_NAND_EVTER_INTR_WPERIR_EN,
|
||||
&ifc->ifc_nand.nand_evter_intr_en);
|
||||
priv->mtd.name = kasprintf(GFP_KERNEL, "%x.flash", (unsigned)res.start);
|
||||
if (!priv->mtd.name) {
|
||||
ret = -ENOMEM;
|
||||
|
|
|
|||
Loading…
Reference in New Issue