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ASoC: q6dsp: q6afe: add codec lpass clocks 

LPASS now has integrated codec control whose clocks are controlled by Q6DSP.
This patch adds support to those clocks.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20200910101732.23484-8-srinivas.kandagatla@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Srinivas Kandagatla 2020-09-10 11:17:31 +01:00 committed by Mark Brown
parent 84ab3b9f19
commit 0c3e35fc1e
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GPG Key ID: 24D68B725D5487D0
2 changed files with 35 additions and 0 deletions
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24
sound/soc/qcom/qdsp6/q6afe.c
View File

@ -359,6 +359,7 @@
#define TIMEOUT_MS 1000
#define AFE_CMD_RESP_AVAIL 0
#define AFE_CMD_RESP_NONE 1
#define AFE_CLK_TOKEN 1024
struct q6afe {
struct apr_device *apr;
@ -887,6 +888,9 @@ static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data)
port->result = *res;
wake_up(&port->wait);
kref_put(&port->refcount, q6afe_port_free);
} else if (hdr->token == AFE_CLK_TOKEN) {
afe->result = *res;
wake_up(&afe->wait);
}
break;
default:
@ -1094,6 +1098,25 @@ static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port,
sizeof(*cfg));
}
int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri,
int clk_root, unsigned int freq)
{
struct q6afe *afe = dev_get_drvdata(dev->parent);
struct afe_clk_set cset = {0,};
cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
cset.clk_id = clk_id;
cset.clk_freq_in_hz = freq;
cset.clk_attri = attri;
cset.clk_root = clk_root;
cset.enable = !!freq;
return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET,
AFE_MODULE_CLOCK_SET, sizeof(cset),
AFE_CLK_TOKEN);
}
EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock);
int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
int clk_src, int clk_root,
unsigned int freq, int dir)
@ -1130,6 +1153,7 @@ int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR:
case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1:
case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT:
case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK:
cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET;
cset.clk_id = clk_id;
cset.clk_freq_in_hz = freq;

11
sound/soc/qcom/qdsp6/q6afe.h
View File

@ -133,6 +133,15 @@
/* Clock ID for INT MCLK1 */
#define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306
#define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309
#define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a
#define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c
#define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d
#define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e
#define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f
#define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b
#define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310
#define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2
#define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3
#define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4
@ -224,6 +233,8 @@ void q6afe_cdc_dma_port_prepare(struct q6afe_port *port,
int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id,
int clk_src, int clk_root,
unsigned int freq, int dir);
int q6afe_set_lpass_clock(struct device *dev, int clk_id, int clk_src,
int clk_root, unsigned int freq);
int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,
char *client_name, uint32_t *client_handle);
int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id,