clk: sunxi-ng: h3: Fix audio clock divider offset
The code had a typo and got the wrong offset for the hardcoded divider, fix that. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reported-by: Jean-Francois Moine <moinejf@free.fr> Reported-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Michael Turquette <mturquette@baylibre.com> Link: lkml.kernel.org/r/20160711203448.18062-1-maxime.ripard@free-electrons.com
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@ -817,8 +817,8 @@ static void __init sun8i_h3_ccu_setup(struct device_node *node)
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/* Force the PLL-Audio-1x divider to 4 */
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val = readl(reg + SUN8I_H3_PLL_AUDIO_REG);
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val &= ~GENMASK(4, 0);
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writel(val | 3, reg + SUN8I_H3_PLL_AUDIO_REG);
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val &= ~GENMASK(19, 16);
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writel(val | (3 << 16), reg + SUN8I_H3_PLL_AUDIO_REG);
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sunxi_ccu_probe(node, reg, &sun8i_h3_ccu_desc);
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}
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