rtlwifi: rtl8192c: rtl8192ce: Add support for B-CUT version of RTL8188CE
Realtek devices with designation RTL8188CE-VL have the so-called B-cut of the wireless chip. This patch adds the special programming needed by these devices. In addition, a variable that was static has been moved into the private data area as it is now needed in two different routines. This change also fixes a minor bug that would be present if a system had more than one RTL81{88,92}CE devices. Other drivers in the rtlwifi family had already made this change, thus the variable already exists in the private data structure. Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net> Cc: Anisse Astier <anisse@astier.eu> Cc: Li Chaoming <chaoming_li@realsil.com.cn> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -724,6 +724,26 @@ u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
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}
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EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
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static void _rtl92c_phy_sw_rf_setting(struct ieee80211_hw *hw, u8 channel)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
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if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
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if (channel == 6 && rtlphy->current_chan_bw ==
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HT_CHANNEL_WIDTH_20)
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rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
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0x00255);
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else{
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u32 backupRF0x1A = (u32)rtl_get_rfreg(hw, RF90_PATH_A,
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RF_RX_G1, RFREG_OFFSET_MASK);
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rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
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backupRF0x1A);
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}
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}
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}
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static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
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u32 cmdtableidx, u32 cmdtablesz,
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enum swchnlcmd_id cmdid,
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@ -837,6 +857,7 @@ bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
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currentcmd->para1,
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RFREG_OFFSET_MASK,
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rtlphy->rfreg_chnlval[rfpath]);
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_rtl92c_phy_sw_rf_setting(hw, channel);
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}
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break;
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default:
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@ -116,6 +116,9 @@
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LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
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#define CHIP_VER_B BIT(4)
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#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
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#define CHIP_BONDING_92C_1T2R 0x1
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#define RF_TYPE_1T2R BIT(1)
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#define CHIP_92C_BITMASK BIT(0)
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#define CHIP_UNKNOWN BIT(7)
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#define CHIP_92C_1T2R 0x03
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@ -896,7 +896,6 @@ int rtl92ce_hw_init(struct ieee80211_hw *hw)
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struct rtl_phy *rtlphy = &(rtlpriv->phy);
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struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
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struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
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static bool iqk_initialized; /* initialized to false */
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bool rtstatus = true;
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bool is92c;
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int err;
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@ -921,9 +920,28 @@ int rtl92ce_hw_init(struct ieee80211_hw *hw)
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rtlhal->last_hmeboxnum = 0;
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rtl92c_phy_mac_config(hw);
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/* because last function modify RCR, so we update
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* rcr var here, or TP will unstable for receive_config
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* is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
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* RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
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rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
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rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
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rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
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rtl92c_phy_bb_config(hw);
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rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
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rtl92c_phy_rf_config(hw);
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if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
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!IS_92C_SERIAL(rtlhal->version)) {
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rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
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rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
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} else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
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rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
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rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
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rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
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rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
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rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
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rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
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}
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rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
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RF_CHNLBW, RFREG_OFFSET_MASK);
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rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
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@ -945,11 +963,11 @@ int rtl92ce_hw_init(struct ieee80211_hw *hw)
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if (ppsc->rfpwr_state == ERFON) {
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rtl92c_phy_set_rfpath_switch(hw, 1);
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if (iqk_initialized) {
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if (rtlphy->iqk_initialized) {
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rtl92c_phy_iq_calibrate(hw, true);
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} else {
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rtl92c_phy_iq_calibrate(hw, false);
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iqk_initialized = true;
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rtlphy->iqk_initialized = true;
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}
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rtl92c_dm_check_txpower_tracking(hw);
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@ -1004,6 +1022,13 @@ static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
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? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
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CHIP_VENDOR_UMC));
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}
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if (IS_92C_SERIAL(version)) {
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value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
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version = (enum version_8192c)(version |
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((CHIP_BONDING_IDENTIFIER(value32)
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== CHIP_BONDING_92C_1T2R) ?
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RF_TYPE_1T2R : 0));
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}
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}
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switch (version) {
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@ -1019,12 +1044,30 @@ static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
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case VERSION_A_CHIP_88C:
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versionid = "A_CHIP_88C";
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break;
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case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
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versionid = "A_CUT_92C_1T2R";
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break;
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case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
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versionid = "A_CUT_92C";
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break;
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case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
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versionid = "A_CUT_88C";
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break;
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case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
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versionid = "B_CUT_92C_1T2R";
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break;
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case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
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versionid = "B_CUT_92C";
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break;
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case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
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versionid = "B_CUT_88C";
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break;
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default:
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versionid = "Unknown. Bug?";
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break;
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}
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RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
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RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
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"Chip Version ID: %s\n", versionid);
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switch (version & 0x3) {
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@ -1197,6 +1240,7 @@ static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
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struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
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u8 u1b_tmp;
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u32 u4b_tmp;
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@ -1225,7 +1269,8 @@ static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
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rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
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rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
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rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
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rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
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if (!IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version))
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rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
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if (rtlpcipriv->bt_coexist.bt_coexistence) {
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u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
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u4b_tmp |= 0x03824800;
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@ -1254,6 +1299,9 @@ void rtl92ce_card_disable(struct ieee80211_hw *hw)
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rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
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RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
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_rtl92ce_poweroff_adapter(hw);
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/* after power off we should do iqk again */
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rtlpriv->phy.iqk_initialized = false;
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}
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void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
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@ -1912,6 +1960,8 @@ static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
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ratr_bitmap &= 0x0f0ff0ff;
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break;
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}
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sta_entry->ratr_index = ratr_index;
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RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
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"ratr_bitmap :%x\n", ratr_bitmap);
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*(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
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@ -82,6 +82,8 @@ bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
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if (is92c)
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rtl_write_byte(rtlpriv, 0x14, 0x71);
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else
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rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
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return rtstatus;
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}
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@ -162,12 +162,10 @@ int rtl92c_init_sw_vars(struct ieee80211_hw *hw)
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/* request fw */
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if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
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!IS_92C_SERIAL(rtlhal->version)) {
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!IS_92C_SERIAL(rtlhal->version))
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rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU.bin";
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} else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
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else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version))
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rtlpriv->cfg->fw_name = "rtlwifi/rtl8192cfwU_B.bin";
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pr_info("****** This B_CUT device may not work with kernels 3.6 and earlier\n");
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}
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rtlpriv->max_fw_size = 0x4000;
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pr_info("Using firmware %s\n", rtlpriv->cfg->fw_name);
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@ -127,11 +127,11 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
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{
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struct rtl_priv *rtlpriv = rtl_priv(hw);
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struct phy_sts_cck_8192s_t *cck_buf;
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struct rtl_ps_ctl *ppsc = rtl_psc(rtlpriv);
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s8 rx_pwr_all = 0, rx_pwr[4];
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u8 evm, pwdb_all, rf_rx_num = 0;
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u8 i, max_spatial_stream;
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u32 rssi, total_rssi = 0;
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bool in_powersavemode = false;
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bool is_cck_rate;
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is_cck_rate = RX_HAL_IS_CCK_RATE(pdesc);
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@ -147,7 +147,7 @@ static void _rtl92ce_query_rxphystatus(struct ieee80211_hw *hw,
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u8 report, cck_highpwr;
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cck_buf = (struct phy_sts_cck_8192s_t *)p_drvinfo;
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if (!in_powersavemode)
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if (ppsc->rfpwr_state == ERFON)
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cck_highpwr = (u8) rtl_get_bbreg(hw,
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RFPGA0_XA_HSSIPARAMETER2,
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BIT(9));
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