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drm: rcar-du: Calculate DPLLCR to be more small jitter 

In general, PLL has VCO (= Voltage controlled oscillator),
one of the very important electronic feature called as "jitter"
is related to this VCO.
In academic generalism, VCO should be maximum to be more small jitter.
In high frequency clock, jitter will be large impact.
Thus, selecting Hi VCO is general theory.

   fin                                 fvco        fout      fclkout
in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
             +-> |  |                             |
             |                                    |
             +-----------------[1/N]<-------------+

	fclkout = fvco / P / FDPLL -- (1)

In PD, it will loop until fin/M = fvco/P/N

	fvco = fin * P *  N / M -- (2)

(1) + (2) indicates

	fclkout = fin * N / M / FDPLL

In this device, N = (n + 1), M = (m + 1), P = 2, FDPLL = (fdpll + 1).

	fclkout = fin * (n + 1) / (m + 1) / (fdpll + 1)

This is the datasheet formula.
One note here is that it should be 2kHz < fvco < 4096MHz
To be smaller jitter, fvco should be maximum,
in other words, N as large as possible, M as small as possible driver
should select. Here, basically M=1.
This patch do it.

Reported-by: HIROSHI INOSE <hiroshi.inose.rb@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[Small clarifications in comments, renamed finnm to fout]
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
Kuninori Morimoto 2017-12-18 00:35:56 +00:00 committed by Laurent Pinchart
parent b45c138502
commit 0bc69592ab
1 changed files with 45 additions and 4 deletions
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49
drivers/gpu/drm/rcar-du/rcar_du_crtc.c
View File

@ -125,13 +125,54 @@ static void rcar_du_dpll_divider(struct rcar_du_crtc *rcrtc,
unsigned int m;
unsigned int n;
for (n = 39; n < 120; n++) {
for (m = 0; m < 4; m++) {
/*
* fin fvco fout fclkout
* in --> [1/M] --> |PD| -> [LPF] -> [VCO] -> [1/P] -+-> [1/FDPLL] -> out
* +-> | | |
* | |
* +---------------- [1/N] <------------+
*
* fclkout = fvco / P / FDPLL -- (1)
*
* fin/M = fvco/P/N
*
* fvco = fin * P * N / M -- (2)
*
* (1) + (2) indicates
*
* fclkout = fin * N / M / FDPLL
*
* NOTES
* N : (n + 1)
* M : (m + 1)
* FDPLL : (fdpll + 1)
* P : 2
* 2kHz < fvco < 4096MHz
*
* To minimize the jitter,
* N : as large as possible
* M : as small as possible
*/
for (m = 0; m < 4; m++) {
for (n = 119; n > 38; n--) {
/*
* This code only runs on 64-bit architectures, the
* unsigned long type can thus be used for 64-bit
* computation. It will still compile without any
* warning on 32-bit architectures.
*
* To optimize calculations, use fout instead of fvco
* to verify the VCO frequency constraint.
*/
unsigned long fout = input * (n + 1) / (m + 1);
if (fout < 1000 || fout > 2048 * 1000 * 1000U)
continue;
for (fdpll = 1; fdpll < 32; fdpll++) {
unsigned long output;
output = input * (n + 1) / (m + 1)
/ (fdpll + 1);
output = fout / (fdpll + 1);
if (output >= 400 * 1000 * 1000)
continue;